FPGA Ethernet PHY and Retimer Selection Guide

First decide whether the board needs a PHY or a retimer #

“Ethernet PHY” and “retimer” are often placed in the same schematic search, but they solve different problems. A PHY terminates a defined Ethernet physical interface and may provide auto-negotiation, link training, cable diagnostics, timing or MACsec. A retimer is a mid-channel signal conditioner: it recovers the clock, reshapes the waveform and launches a cleaner serial signal. It does not turn an arbitrary FPGA transceiver stream into a standards-compliant copper or optical Ethernet port.

That boundary matters now because current FPGA families integrate much more of the Ethernet stack. AMD Versal MRMAC and Altera Agilex 7 F-Tile devices can place MAC, PCS, FEC and high-speed PMA functions inside the FPGA package. Altera's F-Tile 26.1.1 documentation, updated in August 2026, spans 10 GbE through 400 GbE profiles and several NRZ/PAM4 lane maps. The external component is therefore selected from the remaining physical problem—not from the port's headline aggregate rate.

For a practical design review, start with one sentence: the FPGA presents this electrical interface and lane map; the board must reach this medium or module through this measured channel.

If that sentence names RGMII or SGMII on one side and 1000BASE-T twisted pair on the other, the board needs a copper PHY. If it names matched 25.78125 Gb/s lanes between an FPGA PMA and a QSFP28 module, a retimer may be needed only when the channel budget or jitter allocation demands it. If it names 10GBASE-KR, precision timing or MACsec, a serial Ethernet PHY can own protocol functions that a transparent retimer cannot.

The FPGA clock-tree guide explains reference-clock jitter and distribution. The optical-transceiver sourcing guide covers module reach, wavelength and supplier qualification. This article owns the electrical and protocol boundary between the FPGA pins and that external medium.

Freeze the Ethernet stack and lane map #

Do not release a schematic with a block labelled only “100G PHY.” Record which layer lives in each device. MAC, PCS, FEC, PMA and PMD are separate ownership decisions, even when a vendor markets them as one subsystem.

Aggregate rate is not a part-selection parameter. “400G” can describe eight approximately 53 Gb/s PAM4 lanes or four approximately 106 Gb/s PAM4 lanes, among other host and media mappings. Altera's current F-Tile architecture makes that distinction explicit: FGT PMAs cover NRZ to 32 Gb/s and PAM4 to 58.125 Gb/s, while FHT PMAs extend to 96–116 Gb/s PAM4. A 56 Gb/s-class retimer can fit the former lane class but not the latter merely because both systems carry 400 GbE traffic.

The FPGA package and speed grade also constrain the answer. Confirm which PMAs bond out, which lanes can share a PLL, whether Ethernet hard IP consumes those lanes, and whether the requested FEC and PTP options fit the selected tile. AMD's current Versal MRMAC guide likewise separates its AXI4-Stream client side, Flex Port/PHY-facing modes and supported GTY, GTYP or GTM transceivers. A block diagram copied from another device or tool release is not pinout approval.

Choose a copper or serial Ethernet PHY for protocol ownership #

A copper PHY is mandatory when an FPGA MAC must drive 10BASE-Te, 100BASE-TX or 1000BASE-T over magnetics and twisted pair. It owns analog line transmission, receive equalization, auto-negotiation and link status. The MAC-side interface then determines FPGA I/O and timing.

TI currently lists DP83867CRRGZR as an active 48-pin, 7 × 7 mm VQFN 1000BASE-T PHY for 0°C to 70°C with RGMII. DP83867ISRGZR is the active industrial-temperature variant with RGMII and SGMII and a −40°C to +85°C range. These are not interchangeable BOM lines: CR versus IS changes the MAC interface and temperature boundary, while the final R/T suffix changes reel quantity. RGMII timing also requires the PCB and register configuration to agree on whether delays are inserted by the MAC, PHY or traces.

At 10G, an external serial PHY can own more than analog reach. Microchip lists VSC8258YMR-01 in production as a four-port 1G/10G serial Ethernet PHY in a 17 × 17 mm, 256-pin FCBGA. Its documented host/line functions include XFI/SFI, 10GBASE-R/W, dual-sided 10GBASE-KR behavior, IEEE 1588 timing and MACsec. That device belongs in a design that needs those protocol and timing functions. It should not be reduced to “a stronger retimer,” and a transparent retimer should not be substituted when the system relies on its training, security or timing state.

For either PHY class, freeze:

• host interface, bus width, voltage and reference-clock ownership;
• line medium, reach, magnetics or module specification;
• auto-negotiation, link-training, FEC and loopback modes;
• MDIO address, strap state, reset timing and production register image;
• PTP timestamp point and latency compensation when time accuracy matters;
• MACsec key ownership and failure policy when security is enabled;
• temperature grade, package, packing code and vendor lifecycle status.

Add a retimer only after the channel budget says so #

A retimer is justified when the passive channel between two otherwise compatible serial endpoints cannot meet the receive eye and jitter budget with acceptable production margin. It is not a substitute for stack definition.

Build the passive model from the actual FPGA package breakout, vias, trace lengths, connectors, cage, cable or backplane, and the module host connector. Include manufacturing variation, crosstalk and temperature. Then compare the loss at the relevant Nyquist frequency with the transmitter, receiver and signal-conditioner capabilities. Placement matters: a CDR device resets the jitter budget at its location, so two shorter controlled channels replace one long channel.

TI lists DS280DF810ABVR as an active, production, eight-channel retimer in an 8 × 13 mm, 135-ball FCCSP for −40°C to +85°C. Its channels lock from 20.2 to 28.4 Gb/s plus documented subrates, and it provides adaptive CTLE/DFE, a transmit FIR, CDR, eye monitor and PRBS generator/checker. That makes it a concrete option for matched 25G-class lanes and QSFP28-era 100G paths, subject to the exact interface mode.

TI's active DS560DF810ALUT is an eight-channel 56 Gb/s-class retimer in the same 8 × 13 mm body class. It supports NRZ and PAM4 symbol rates from 19.6 to 28.9 GBd, adds RX FFE/DFE, TX FFE, eye/PRBS diagnostics and optional NRZ/PAM4 gearbox behavior. It can serve documented 400 GbE lane arrangements, but it does not cover a four-lane 106.25 GBd host interface. The full OPN also matters: ALUT is the 250-piece tape-and-reel option; ALUR is the 1,000-piece option.

Three boundaries often disqualify an otherwise attractive retimer:

• Link training. TI's 25G/28G selection note distinguishes redrivers that

pass training amplitude information from retimers that do not implement the standard's training logic. A backplane that depends on Clause 72 training must be reviewed as an end-to-end system, not only as a loss budget.

• Modulation and gearbox ownership. NRZ and PAM4 specifications use symbol

rate as well as bit rate. Confirm whether conversion occurs in the FPGA, retimer, module or external PHY.

• FEC transparency versus termination. A retimer may pass a coded serial

stream, while a PHY or FPGA block may terminate and regenerate FEC. Error counters must be read at the layer that owns the codeword.

Treat clocks, firmware and power as part of the link #

An Ethernet channel does not end at the differential pairs. The release design also includes reference clocks, reset, low-speed management and power.

Use the FPGA and external-device data sheets to allocate reference-clock frequency, jitter, spread-spectrum policy and startup sequence. A retimer with CDR may not require an external low-jitter reference for data recovery, but its management clock, EEPROM boot and reset still have timing requirements. A PHY may generate a recovered or synchronized clock, yet that output is useful only when the receiving logic, jitter transfer and PTP architecture explicitly use it.

Archive the complete initialization image. Strap-only defaults are rarely enough for a high-speed production link. Record the MDIO/I²C transactions, firmware version, EEPROM checksum, lane polarity and crosspoint mapping, TX preset, adaptation settings, interrupt masks and fault-recovery policy. If the FPGA supports runtime reconfiguration, define which settings may change without resetting the far-end module or corrupting traffic.

Power integrity is also visible as link margin. Budget each supply, place the required decoupling, and check startup at minimum and maximum ramp. Retimer and PHY junction temperature should be measured in the real airflow; adaptive equalization cannot compensate for a device operating outside its temperature or supply limits.

Validate from analog channel to Ethernet counters #

PRBS success in transceiver loopback is necessary but not sufficient. It can bypass the external PHY, module, training state or FEC path that the product actually uses. Validation should advance through observable layers and keep the same lane map, clock plan and firmware image used by production.

Run the tests in both directions. One marginal receive lane can hide behind aggregate packet counters, while one swapped transmit pair can be corrected by a lab instrument but not by the production module. Capture per-lane evidence before bonding and FEC combine the result.

For a retimed design, compare three configurations on representative hardware: the intended retimer settings, a bypass or direct path where physically available, and stressed loss/jitter. This reveals whether the device adds real margin or merely changes where the failure appears. Repeat after thermal soak and with the exact production cage, connector and module.

Release the FPGA, PHY or retimer as one controlled interface #

An RFQ for “one 100G retimer” is not actionable. The controlled BOM packet should contain:

• FPGA family, full OPN, package, speed grade and Ethernet IP/tool version;
• aggregate port rate, per-lane rate, lane count, NRZ/PAM4 mode and FEC;
• host and line interface names, medium, module form factor and reach;
• full PHY or retimer OPN, package, grade, packing quantity and configuration image;
• channel-loss model, connector/cage revision and approved PCB stack-up;
• required diagnostics, PTP, MACsec, training, gearbox and failover functions;
• qualified module/cable list and the lab evidence used to approve each item;
• substitution rule that identifies which changes require SI, protocol, environmental or security requalification.

Do not approve a substitute from channel count and maximum data rate alone. Pin-compatible signal conditioners can differ in CDR behavior or link-training support; PHY variants can differ in MAC interface, temperature range, timing or security. Purchasing should compare the exact orderable code against the controlled interface, not against a distributor's abbreviated description.

Conclusion #

Use an Ethernet PHY when the board needs media termination or protocol ownership: twisted-pair conversion, auto-negotiation, link training, timing or MACsec. Use a retimer only when two already compatible high-speed endpoints need a measured signal-integrity and jitter reset. Use neither when the FPGA-to-module channel already closes with production margin.

The defensible selection starts with the FPGA's exact MAC/PCS/FEC/PMA profile, then freezes the per-lane electrical contract, medium and validation evidence. Only after that work should the BOM name DP83867CRRGZR, DP83867ISRGZR, VSC8258YMR-01, DS280DF810ABVR, DS560DF810ALUT or another qualified device.

Official references #

• AMD Versal Integrated 100G Multirate Ethernet MAC Subsystem PG314, version 3.1
• AMD UltraScale+ Integrated 100G Ethernet Subsystem PG203, version 3.1
• Altera F-Tile Architecture and PMA/FEC Direct PHY User Guide 26.1
• Altera F-Tile Ethernet Hard IP User Guide 26.1.1
• TI DP83867CR product page and active lifecycle position
• TI DP83867IS product page, RGMII/SGMII and industrial-temperature position
• Microchip VSC8258 product page and in-production status
• Microchip VSC8258-01 datasheet and VSC8258YMR-01 ordering information
• TI DS280DF810 product page, active status and signal-conditioning features
• TI DS560DF810 product page, active status and PAM4/NRZ operating range
• TI application note: Optimal Implementation of 25G/28G Retimers versus Redrivers