FPGA JESD204B/C ADC Interface Design Guide

Freeze the converter mode before choosing the FPGA #

A high-speed ADC does not present a generic “JESD204” stream. It presents one of a finite set of transport modes, each fixing the number of virtual converters, sample width, number of lanes, lane rate, link count, encoding and synchronization behavior. The FPGA must implement that exact contract. Selecting an FPGA because it has “enough transceivers” and resolving the converter mode later is a common way to discover that the chosen speed grade, transceiver bank, reference clock or IP configuration cannot close the link.

The release sequence should therefore be:

1. choose the ADC operating mode, including DDC and decimation; 2. copy the manufacturer-defined JESD parameters into a controlled interface sheet; 3. calculate lane rate and check it against both endpoints with margin; 4. place the lanes, reference clocks and SYSREF on the FPGA; 5. generate the vendor IP and its example design for that same mode; and 6. prove link integrity, sample mapping and deterministic latency on hardware.

This guide is for FPGA and high-speed-converter engineers who own that interface, and for BOM teams who must preserve the exact ADC, FPGA capability and evaluation evidence behind it. The companion FPGA clock-tree design guide covers how to generate low-jitter device clocks and a coherent SYSREF. Here the focus begins at the ADC transport mapper and ends at correctly ordered samples in FPGA fabric.

Treat the JESD mode as a versioned interface contract #

For every candidate mode, record at least L (lanes), M (virtual converters), F (octets per frame per lane), S (samples per converter per frame), N (converter resolution), N' (transmitted sample width), subclass, scrambling, link count and encoding. JESD204C 64B/66B modes also require the applicable multiblock and extended-multiblock parameters. If the ADC has DDCs, record the real or complex output format, decimation, NCO profile and sample ordering—not only the physical ADC sample rate.

For a straightforward real-output mode, the serial-rate cross-check is:

lane rate = output sample rate × M × N' ÷ L × encoding overhead

Use 10/8 for 8B/10B and 66/64 for 64B/66B. This is a cross-check, not a license to invent a converter mode. Integrated RF ADCs can add complex data, control bits, multiple links and restricted parameter combinations. The converter data sheet or mode-selection tool remains authoritative.

The distinction between B and C is more precise than “old versus fast.” JESD204B uses 8B/10B link coding. JESD204C retains an 8B/10B option and adds 64B/66B, whose lower coding overhead supports higher useful throughput; C also defines link features such as multiblock alignment and optional error protection. The chosen ADC mode and FPGA IP must agree on the actual coding. A C-capable part configured for 8B/10B does not become a 64B/66B link merely because both endpoints advertise JESD204C.

Keep this sheet beside the ADC register image, FPGA IP configuration, constraint set and firmware version. A register change that selects another JMODE or ADI mode number is an interface change even when the schematic is untouched.

Select B or C from the endpoint limits, not preference #

JESD204B remains a valid choice when the approved ADC exposes B, the resulting lane rate fits a qualified FPGA transceiver, and the project values an existing IP and validation base. Analog Devices still marks the 10.25 GSPS AD9213BBPZ-10G as recommended for new designs; it uses up to 16 JESD204B lanes at up to 16 Gbps. Its 6 GSPS counterpart is AD9213BBPZ-6G. A team with a released AD9213 design should not convert it to C simply to modernize a label: the ADC itself is a B endpoint, so that change means a converter and system redesign.

JESD204C becomes compelling when converter throughput would otherwise consume too many B lanes, when a current converter mode is defined around 64B/66B, or when the chosen FPGA tile and IP are already qualified at the required rate. Two current examples show why the mode table matters:

ADI's AD9209 page also provides a mode selector, frame-mapping tool and companion transport RTL generator. Those are useful evidence, but generated RTL does not waive FPGA timing closure or interoperability testing. TI's ADC12DJ5200RF data sheet similarly defines the allowed JMODE combinations; configurations outside that table are not supported modes assembled from otherwise legal numbers.

Do not compare lane rate with the FPGA's absolute transceiver maximum alone. Confirm the selected family and speed grade, the exact GT or F-Tile capability, the number of available channels after PCIe/Ethernet allocations, PLL sharing, reference-clock range, bonding rules, package pins and the vendor IP's supported rate. Reserve debug access and board-loss margin before the pinout is frozen.

Map the FPGA receive path in layers #

An ADC receive design contains four separate layers that should remain visible in the block design and debug plan:

• Transceiver/PHY: termination, equalization, CDR, serial-to-parallel

conversion, lane polarity and physical alignment.

• JESD link layer: code-group or sync-header lock, lane alignment,

scrambling, error detection and elastic buffering.

• Transport layer: mapping lane octets or blocks back into converter samples,

channels and control bits.

• Application layer: framing captured samples into DSP, DMA or memory while

preserving timestamp and overrange information.

AMD's JESD204C v4.3 core presents 4 bytes per lane per core cycle in 8B/10B mode and 8 bytes per lane per cycle in 64B/66B mode. That difference changes core-clock rate and fabric width; it is not hidden by the serial transceiver. For Versal devices, the generated design shares a Versal transceiver or GT Wizard subsystem; for UltraScale/UltraScale+ it can use the JESD204 PHY. AMD explicitly treats the example design as a starting point rather than coverage of every configuration.

Altera's November 2025 AN 1014 adds another current boundary: its Agilex 7 F-Tile JESD204C design scales a single-link example into synchronized dual links. The note requires identical parameters for the links and shows that multi-link support affects Platform Designer instances, top-level HDL, reset connections, pin assignments and SDC constraints. It is evidence for a method, not proof that an arbitrary ADC board has been validated with an arbitrary Agilex device.

SYSREF proves repeatability only after the data path is healthy #

Subclass 1 uses SYSREF to align the local timing boundaries at the ADC and FPGA. For JESD204B/8B10B this is associated with the local multiframe clock (LMFC); for JESD204C 64B/66B it is the local extended multiblock clock (LEMC). SYSREF cannot repair a lane-rate, encoding or transport mismatch. First obtain a clean physical link, then prove its data mapping, and only then judge deterministic latency.

AMD's current PG242 requires SYSREF to be captured synchronously to the core clock. Its permitted period must be a multiple of four-byte clock periods for 8B/10B and eight-byte clock periods for 64B/66B. AMD also exposes status for SYSREF capture and out-of-phase detection. The ADC has its own setup/hold window, divider and subclass restrictions, so the final SYSREF frequency and phase must satisfy both endpoints and the clock device.

Multi-ADC systems add another constraint: common clocks do not guarantee a common sample epoch unless device synchronization, NCO synchronization, link alignment and application timestamps are all included in the test. Measure channel-to-channel phase after repeated power cycles and link resets. A single successful boot is not deterministic-latency evidence.

Bring up the link as six observable gates #

The fastest debug method is to stop at the first failed layer. Do not rewrite ADC registers and FPGA constraints simultaneously.

1. Clock gate: verify ADC device clock, FPGA transceiver reference clock and core clock at their receivers. Confirm PLL lock and expected frequency before releasing the JESD blocks. 2. Transceiver gate: use a supported ADC test pattern or loopback to obtain CDR lock, stable disparity/error counts or sync-header lock on every enabled lane. Check polarity, lane placement, insertion loss and equalization here. 3. Link gate: for 8B/10B, observe code-group synchronization, SYNC behavior and ILA contents. For 64B/66B, observe sync-header and multiblock lock plus CRC/FEC counters when the selected mode supports them. 4. Transport gate: compare received configuration with the controlled mode sheet, then verify ramp and repeated-pattern data. Confirm lane mapping, sample width, sign, channel order and overrange bits before using live RF input. 5. Latency gate: issue the documented SYSREF sequence and repeat link resets and power cycles. Record LMFC/LEMC position and end-to-end sample latency. 6. Application gate: run full-rate capture into the real DSP/DMA/memory path, with long-duration error counters, temperature corners and simultaneous system traffic. A link that works only with an on-chip analyzer attached is unfinished.

Keep the first-failure evidence. “No samples” is not a useful defect report; “all eight lanes have CDR lock, lane 3 accumulates sync-header errors, SYSREF has not yet been enabled” points to a physical-lane problem and prevents unrelated firmware changes.

BOM, layout and RFQ controls #

The converter line item alone does not preserve the interface. Release the ADC and FPGA as an evidence group containing:

• full ADC order code, speed option, package, packing format and temperature grade;
• FPGA family, full device code and speed grade with the allocated transceiver tiles;
• clock generator, oscillator/VCXO and the production register image;
• ADC register/API release, JMODE or mode number and checksum;
• FPGA tool and JESD IP versions, generated configuration and license status;
• evaluation boards, adapters and cable assemblies used for interoperability work;
• schematic lane map, polarity inversions, reference-clock pins and SYSREF routing;
• link test report covering BER/error counters, resets, latency and temperature.

Neither AD9209BBPZRL-4G nor ADC12DJ5200RFAAVT should be shortened to the base family in an RFQ. Packing suffixes affect receiving and assembly; speed and package codes can change the electrical design. Conversely, a tray-versus-reel change is not automatically permission to replace the silicon model or speed grade. State which packing alternatives are commercially acceptable and which component changes require engineering approval.

For PCB review, treat every lane as part of a bonded group. Maintain the FPGA and ADC reference planes, avoid stubs, preserve AC-coupling and termination assumptions, and simulate the complete channel with package and connector models when the rate requires it. The clock and SYSREF routes need their own skew and noise constraints; they are not spare low-speed nets simply because their frequencies are below the serial lanes.

Conclusion #

An FPGA-to-ADC JESD204 interface succeeds when one converter mode becomes one controlled implementation: exact ADC registers, exact lane/encoding parameters, qualified transceiver placement, coherent clocks, observable link states and repeatable sample mapping. Choose JESD204B when the approved current converter and qualified lane rate make B the lowest-risk path. Choose JESD204C when a supported converter mode and FPGA tile use its higher-rate or 64B/66B capability for a measurable system benefit. In both cases, release the full order codes and the validation evidence with the BOM; “JESD-compatible” is not an alternate-part approval.

Official references #

• Analog Devices AD9209 product page, orderable models and JESD204B/C tools
• Analog Devices AD9213 product page, JESD204B limits and orderable models
• Texas Instruments ADC12DJ5200RF Rev. G data sheet and July 2026 ordering addendum
• AMD JESD204C v4.3 LogiCORE IP Product Guide: clocking
• AMD JESD204C v4.3 data and command interfaces
• AMD JESD204C v4.3 SYSREF timing requirements
• AMD JESD204C v4.3 example-design scope and architecture
• Altera AN 1014: Agilex 7 F-Tile JESD204C ADC dual-link implementation