Electronic Component Sourcing Guides & Hot Part Notes
Long-life articles for OEM, EMS and engineering buyers: part-number sourcing notes, package checks, date-code verification, BOM risk and quality-control guidance.
How to Read a Component Quote: MOQ, SPQ, Date Code and Allocation Surcharges
A buyer's guide to decoding distributor component quotes—MOQ, SPQ, reel vs cut tape, date-code limits and allocation surcharges that change the real landed cost.
FPGA High-Speed DAC and RF Front-End Design
Turn FPGA samples into a verified RF output: select a JESD204 DAC mode, plan interpolation and clocks, protect the analog path and freeze an RF BOM.
Rockchip RV1126B deep dive — 3 TOPS edge AI vision processor, 35 mm form factor, and why it is driving a wave of sourcing inquiries
A comprehensive engineering guide to Rockchip's RV1126B edge AI SoC — quad Cortex-A53, 3 TOPS NPU, dedicated AI-ISP, AOV 3.0 always-on vision, 35×35 mm module…
Decoupling Capacitor Selection: From Target Impedance to a Buildable BOM
How to size a decoupling network by target impedance, derate MLCCs for DC bias, control mounting inductance, and turn the result into capacitor ordering codes you can…
FPGA JESD204B/C ADC Interface Design Guide
Design an FPGA-to-ADC JESD204B/C link: calculate lane rate, match transport modes, plan SYSREF, debug synchronization and lock exact BOM codes.
OCP ORv3 48V Rack Power: Shelf, Busbar, BBU and PMI
Design an OCP ORv3 48V rack power chain: size the N+1 shelf, busbar interface, BBU ride-through, PMI controls and exact connector BOM.
54V AI Server Hot-Swap and Backplane Protection
Design 54V AI-server input protection: control inrush, protect backplanes, verify MOSFET SOA and specify current hot-swap controller order codes.
AI Server Power Semiconductors in 2026: SiC, GaN, DrMOS and PMIC Under Supply Pressure
A 2026 procurement view of AI-server power semiconductors — SiC, GaN, DrMOS and PMIC supply pressure, price-cycle signals, 800V HVDC impact and buyer checks.
FPGA Clock Tree Design: Jitter, PLLs and SYSREF
Design an FPGA clock tree for high-speed converters: budget jitter, choose dual-loop PLLs, align SYSREF and lock exact clock IC order codes.
LDO vs Switching Regulator: How to Choose the Right Power Stage for Each Rail
A practical engineering guide to choosing between LDO and switching regulators for each power rail—efficiency, noise, BOM cost and the trade-offs that decide which…
RK3588 + CODESYS Industrial Soft PLC Design Guide
Evaluate an RK3588 CODESYS soft PLC for EtherCAT, edge AI and industrial control, with architecture, real-time validation and sourcing checks.
Run DeepSeek-R1 Distill Locally on RK3588
Deploy DeepSeek-R1-Distill-Qwen-1.5B on RK3588 with RKLLM, covering W8A8 conversion, memory, runtime setup, benchmarks and board checks.