FPGA PCIe Gen4/Gen5 Clocking and Retimer Design

Freeze the clock architecture before adding a retimer #

An FPGA PCIe link is two coupled contracts: a 100 MHz reference-clock architecture and a bidirectional serial channel. A retimer can recover and relaunch serial data, but it does not make an undefined reference-clock scheme, reset sequence or lane map valid. That distinction becomes more important when moving from PCIe Gen4 at 16 GT/s to Gen5 at 32 GT/s, where the passive reach shrinks and the reference-clock jitter allowance is tighter.

The practical design order is therefore:

1. Select the exact FPGA device, PCIe hard-IP instance, link width and generation. 2. Declare common REFCLK or an independently clocked architecture for every port. 3. Model each passive segment using the real package, PCB, connector and cable. 4. Add a protocol-aware retimer only where the segmented channel needs it. 5. Freeze reset, sideband, firmware, thermal and telemetry ownership. 6. Validate training, margin and recovery with the production clock and lane map.

PCI-SIG describes PCIe 4.0 and 5.0 retimers as Physical Layer protocol-aware devices that participate in link equalization and adjust data rate and width with the two link partners. Up to two retimers are allowed in a link. This is a much narrower role than a PCIe switch, which terminates Data Link and Transaction Layers, and a materially different role from a linear redriver, which remains part of one electrical channel.

The FPGA clock-tree guide covers general jitter budgeting and clock distribution. The FPGA Ethernet PHY and retimer guide explains a different protocol boundary. This article owns the PCIe-specific clock mode, equalization, retimer and bring-up decisions.

Choose common clock or independent clock deliberately #

PCI-SIG's public PCIe 5.0 implementation guidance identifies two clock architectures. In common REFCLK, the root complex, retimer and endpoint receive the same nominal 100 MHz source. Distribution delay means the edges are not physically coincident, but all devices remain tied to one source. In independent REFCLK, the root complex and endpoint use independent sources and the transmitters and receivers must meet the applicable independent-clock requirements.

Terms such as SRNS and SRIS are often used for separate-reference-clock systems without and with independent spread-spectrum clocking. The label alone is not a design. The FPGA IP, retimer, endpoint and clock source must all support the exact mode, and the validation plan must exercise that mode. Do not assume that an endpoint supporting common clock also supports an independently spread clock.

For an open add-in-card system using a commercial root complex or switch, AMD's current Versal DMA and Bridge Subsystem guide directs designers toward synchronous clocking. It accepts a 100, 125 or 250 MHz reference input for the programmable- logic PCIe block, but a standard motherboard PCIe interface is normally built around the 100 MHz system clock. That vendor guidance is an implementation boundary for the named IP—not permission to substitute another frequency at a CEM connector.

Altera's current Agilex 7 F-Tile PCIe guide exposes a different FPGA-side constraint. The F-Tile Reference and System PLL Clocks IP is required, and the selected hard-IP mode determines which package refclk pins can serve each port. A 1x16 mode connects its refclk ports to one F-Tile reference-clock output, whereas bifurcated 2x8, 2x4 and 4x4 modes can use shared or independent sources subject to the documented pin network. The same guide states that PERST# must reflect clock stability for those port arrangements.

The clock worksheet should record these fields per logical link:

PCI-SIG's public Gen5 Q&A states a 0.25 ps RMS reference-clock design limit for the discussed PCIe 5.0 system analysis. That number should not be mixed with a clock-device headline integrated over an unrelated band. Use the compliance method and transfer functions applicable to the selected PCIe clock mode, then measure the production source, buffer, termination and board noise together.

A clock buffer is selected by topology, not output count #

A fanout or zero-delay buffer distributes the chosen clock architecture; it does not create protocol support. Confirm input/output signaling, impedance, termination, SSC tracking, additive jitter, PLL bandwidth, supply and enable behavior at every receiver.

Renesas currently lists the 9ZXL0851E as active and PCIe Gen1–5 compliant. It provides eight LP-HCSL outputs, accepts a spread-spectrum input, offers PLL bandwidth/bypass control and uses a 48-lead 6 mm × 6 mm VFQFPN. The public product table distinguishes four active order codes:

Those suffixes are not purchasing decoration. If a retimer, FPGA and endpoint are spread across a hot accelerator board, the 85°C and 105°C clock-buffer grades create different environmental boundaries. If the design uses direct HCSL rather than LP-HCSL, or requires another output count, the receiver termination and pinout must be reviewed rather than inferred from the DB800ZL family name.

Insert a retimer only where two segment budgets close #

The retimer location splits one logical link into two electrical segments. Each segment includes a transmitter package, breakout, vias, traces, connectors and the receiver package at the retimer or link partner. PCI-SIG's implementation guidance says the insertion-loss budget and compliance work should be performed separately on both sides. Placing the retimer at the geometric midpoint is not the goal; placing it where both independent segments retain margin is.

Start with extracted or measured channels, not a board-length rule. Compare the direct path with the segmented path at process, voltage and temperature corners. Include the retimer package, required AC coupling, power delivery and local thermal rise. The device adds capability but also creates another powered and configured component whose failure can take the link down.

For Gen4, TI's active DS160PT801ACBR is a concrete eight-lane protocol-aware retimer option. It supports 2.5, 5, 8 and 16 GT/s, common clock and separate- reference-clock modes with or without SSC, equalization training, 2x4 bifurcation, eye monitoring and PCIe receiver margining. It uses a 332-ball 8.5 mm × 13.4 mm FCCSP, two supply rails and an SMBus/EEPROM configuration path. DS160PT801ACBT is the 250-piece small-reel carrier; ACBR is the 2,000-piece reel. Two devices and their documented inter-chip connection are required for an x16 Gen4 implementation, so an x16 BOM is not one ACBR line.

For Gen5, Astera Labs publicly lists PT5081 as a production x8 PCIe 5.0/CXL 2.0 retimer and PT5161 as the production x16 version. Its portfolio brief describes automatic link equalization, flexible bifurcation, I2C/I3C management, SPI-flash or EEPROM firmware loading, and per-link history and electrical-margin diagnostics through the COSMOS software suite. These public identifiers are appropriate for an initial RFQ, but the supplier must return the complete protocol-specific orderable suffix, package revision, firmware requirements and commercial status before AVL release.

Do not replace a retimer with a Gen5 linear redriver because the channel count and 32 Gb/s headline match. A redriver can extend a moderate-loss channel while remaining transparent to training. A retimer recovers the embedded clock, creates two electrical segments and participates in PCIe Physical Layer behavior. The choice changes simulation, placement, firmware, thermal design, compliance and interoperability work.

Lane width, polarity and sideband are one configuration #

A protocol-aware retimer must follow the link's negotiated rate and width. PCI-SIG states that upstream and downstream widths must match, although a retimer must support down-configuration. The PCB lane map, FPGA IP, retimer bifurcation and connector definition therefore need one controlled source.

Freeze lane reversal and polarity capabilities before layout. Do not assume a retimer can repair an arbitrary cross-lane permutation. For x16 assembled from two Gen4 x8 devices, confirm the vendor's inter-chip requirements, reset relationship and bifurcation boundary. For a multiport Gen5 retimer, preserve which lanes belong to each independently managed link.

The low-speed design belongs in the same review:

• PERST# timing and distribution to the FPGA endpoint and retimer;
• CLKREQ# and power-state behavior where the form factor uses them;
• SMBus/I2C/I3C address plan, voltage and host ownership;
• EEPROM or flash image, checksum, update and fallback policy;
• interrupt, temperature, link-history and margin telemetry;
• test access that does not add an uncontrolled high-speed stub;
• retimer rails, sequencing, decoupling and worst-case junction temperature.

“Software transparent” does not mean “firmware free.” A retimer does not appear as a packet switch, yet the board still needs a reproducible configuration and a way to diagnose link state across its pseudo ports.

Validate the state machine, not just a clean eye #

PCIe Gen4/Gen5 qualification needs both analog and protocol evidence. A transmitter eye test does not prove receiver tolerance, lane mapping, equalization or recovery. PCI-SIG explicitly recommends exercising the LTSSM and application-specific events such as hot plug; passing TX compliance and receiver BER separately does not guarantee system interoperability.

Use a staged bring-up that leaves an artifact at every boundary:

1. Power and clock: measure every FPGA, retimer and clock-buffer rail; confirm the selected REFCLK mode and SSC behavior at the loaded receivers. 2. Reset release: capture REFCLK stability, PERST# and configuration completion across repeated cold starts and the slowest allowed power ramp. 3. Receiver detect and Polling: verify termination detection, lane polarity and the expected active lane group before blaming equalization. 4. Configuration and equalization: save FPGA LTSSM state, negotiated speed and width, retimer pseudo-port state and per-lane adaptation information. 5. Margin and traffic: run receiver lane margining where supported, protocol error monitoring and sustained application traffic in both directions. 6. Recovery: inject warm reset, link retrain, reference-clock disturbance, power-state transitions and the product's hot-plug events. 7. Corners and population: repeat on representative boards, connector/cable options, temperature, voltage and approved component alternates.

The PCI Express Retimer Test Specification Revision 5.0 is useful supplier evidence for a stand-alone retimer in common-clock mode, but PCI-SIG explicitly limits that document's scope: it does not test a retimer integrated into the customer platform or add-in card. Request the device evidence, then perform the system tests for the actual FPGA, clock mode and topology.

Turn the interface contract into an RFQ #

Procurement should not receive “PCIe Gen5 retimer” or “eight-output PCIe clock” as a complete request. Release the components as one interface group:

Classify alternatives by the requalification they trigger. A packing-only change may be commercially reviewable. A temperature-grade change needs environmental and lifecycle confirmation. A different clock buffer can change signaling, termination and jitter. A different retimer can change pinout, firmware, bifurcation, telemetry, power and interoperability. None of the latter should be approved from distributor parametrics alone.

For 9ZXL0851EKILFT, state whether the −40°C to +85°C reel model is mandatory or whether the higher-temperature 9ZXL0851EKKLFT has been qualified. For DS160PT801ACBR, state the x8 use or the paired-device x16 architecture and preserve the external EEPROM image. For PT5081 or PT5161, require the manufacturer to return the complete suffix and supported firmware package rather than allowing the family identifier to enter production ERP as if it were a full ordering code.

Conclusion #

A robust FPGA PCIe Gen4 or Gen5 design begins by declaring the reference-clock mode, FPGA hard-IP resource, lane map and passive channel. A retimer is added only after that model shows two segments can close with production margin. Clock distribution, retimer firmware, reset, telemetry and thermal limits then become part of the same released interface.

That process turns a vague high-speed-link BOM into an auditable decision: the engineer can explain why the direct path fails or passes, validation can isolate where training stops, and purchasing can quote exact clock and retimer variants without silently changing the clock architecture or link topology.

Official references #

• PCI-SIG FAQ: what retimers are and when they are needed
• PCI-SIG PCIe 5.0 implementation webinar Q&A on clock modes, retimers and validation
• PCI-SIG PCI Express Retimer Test Specification Revision 5.0 scope
• AMD Versal DMA and Bridge Subsystem PG344 clocking guidance
• AMD Versal Integrated Block for PCI Express PG343 clock and reset signals
• Altera F-Tile Avalon Streaming IP for PCI Express 25.3 reference-clock guidance
• Renesas 9ZXL0851E product page, lifecycle and orderable variants
• TI DS160PT801 product page and orderable package options
• TI DS160PT801 Rev. A data sheet
• Astera Labs Aries PCIe/CXL Smart DSP Retimer portfolio and production status
• Astera Labs Aries Smart DSP Retimer portfolio brief