FPGA DDR4 and DDR5 Design: PHY, Layout and BOM

Start with the FPGA memory resource, not a DRAM quotation #

An external DDR interface is not a collection of ordinary FPGA pins. It is a system formed by a particular FPGA ordering code and package, memory-capable I/O banks, controller and PHY IP, reference clocks, board topology, DRAM organization and a calibration sequence. Change one item and the supported rate, pin placement or validation scope may change.

That is why a request for “16 Gb DDR4” or “DDR5-5600” is incomplete. Density and nominal speed do not establish compatibility. The approved part must also match organization, package, speed grade, temperature range, supply architecture and the topology configured in the FPGA tool.

Platform support is not uniform. AMD documents dedicated Versal memory-controller variants for DDR4/LPDDR4 and newer DDR5/LPDDR5 interfaces. Intel's Agilex 7 M-Series EMIF supports DDR4, DDR5 and LPDDR5 with hardened PHY and calibration resources. Other Versal and Agilex families have different boundaries. The exact family, device, package and IP release must therefore be checked.

The companion HBM versus DDR4/DDR5 guide compares architectures. This article focuses on the engineering and sourcing decisions that determine whether an external-memory board boots reliably and remains buildable.

DDR4 versus DDR5 is a platform decision #

DDR5 offers a higher data-rate roadmap and changes several electrical and module-level functions, but it is not a drop-in upgrade for DDR4. A redesign normally touches the FPGA choice, controller IP, I/O bank plan, power tree, PCB stack-up, simulation models and memory BOM.

DDR5 on-die ECC is often misunderstood. It improves correction inside the DRAM die; it does not automatically provide end-to-end system ECC across the FPGA interface. If the application requires bus or system-level fault protection, confirm the controller ECC mode, data width and additional device requirement separately.

Choose DDR5 when bandwidth, density roadmap or platform life justifies the qualification work. DDR4 remains rational when the selected FPGA has a mature DDR4 solution, bandwidth fits comfortably and long-term availability can be controlled through an approved-vendor list.

Match the exact FPGA family, package and controller #

Before schematic capture, record the FPGA OPN, package, speed grade, tool release, controller/PHY version, protocol, rate, width, ECC mode, topology and number of interfaces.

AMD Versal shows why specificity matters. AMD documents DDRMC for DDR4/LPDDR4 and DDRMC5 variants for newer DDR5/LPDDR5 interfaces in supported devices. First-generation and newer Versal devices do not all expose the same standards. UltraScale and UltraScale+ designs obtain their supported configuration through the Memory Interface Generator flow for the selected device and package.

Intel Agilex also spans different capabilities. Agilex 7 M-Series uses hard memory-controller, hard PHY and localized calibration resources for DDR4, DDR5 and LPDDR5. Agilex 7 F- and I-Series documentation describes DDR4 external-memory resources. The exact limit remains device- and IP-dependent.

This matters during FPGA substitution. A larger logic device is not necessarily memory-interface equivalent. Package escape, bank location, dedicated clocks and controller instances can invalidate an apparently attractive alternate.

Freeze width, organization and topology together #

Translate capacity and bandwidth into an actual component arrangement. A 32-bit bus may use two x16 devices or four x8 devices, but those options do not create the same loading, routing, ECC expansion or supply pool. A 64-bit interface with sideband ECC changes device count again.

Discrete DRAM gives direct control of placement and routing. UDIMM, SODIMM, RDIMM and LRDIMM introduce connector, rank, register or buffer behavior and are valid only when the controller explicitly supports that format. Intel's EMIF parameters, for example, distinguish these formats and note that availability varies by protocol and device.

Freeze these items before releasing the schematic:

1. Usable capacity and sustained bandwidth.

2. DQ width, byte-lane count and system ECC requirement.

3. Discrete component or supported module format.

4. Device organization: x4, x8 or x16 as applicable.

5. Rank count and command/address loading.

6. Target rate and a slower bring-up rate.

7. Exact controller preset or custom component parameters.

Matching density while changing x8 to x16, package ballout or rank construction is an engineering change—not a purchasing substitution.

Treat the board channel as part of the PHY #

DDR routing is organized by signal groups, not one universal length number. DQ and DQS are managed in byte lanes; clock, command/address and control signals follow topology-specific rules. The generated constraints and vendor board tables define pin placement, topology, impedance, spacing and timing for the selected interface.

Do not copy a trace-length rule from another family, package or DIMM. Package delay, bank architecture and calibration capability differ. Preserve reference planes, minimize discontinuities and stubs, and model vias, connectors and packages at the intended rate.

Useful pre-layout evidence includes a bank/pin map, byte-lane placement drawing, stack-up and impedance targets, topology diagram, simulation plan and routing report generated from the same IP configuration used by the FPGA build.

The reference clock needs its own ownership record. Use the dedicated resources required by the selected memory bank and verify jitter, tolerance, startup and reset sequence. The FPGA clock-tree guide explains the wider process but does not replace memory-IP requirements.

Training is a margin process, not a repair tool #

Calibration aligns the PHY with the board and DRAM timing. Depending on protocol and controller, it can include initialization, delay calibration, write leveling, read alignment, per-bit deskew and Vref-related training. Use the status and debug outputs exposed by the chosen IP; one “calibration done” bit does not prove production margin.

Training compensates for bounded variation. It cannot rescue an unsupported topology, wrong termination, poor return path or unstable rail. A board that calibrates once at room temperature is not qualified.

A defensible sequence is:

1. Check DRAM and FPGA I/O rails, references, reset and clock before traffic.

2. Confirm controller build, part parameters and board revision.

3. Capture calibration debug after cold start, warm reset and repeated power cycles.

4. Run address, walking-bit, checkerboard, pseudo-random and burst traffic over the full memory range.

5. Repeat at voltage and temperature limits with realistic simultaneous FPGA activity.

6. Record counters, margins, device markings, firmware hash and test conditions.

7. Repeat critical qualification for every alternate DRAM OPN.

Where the controller offers margining tools, save the actual results. Trends across boards and lots are more useful than one golden-board screenshot.

Power integrity can look like a timing defect #

DDR current is dynamic. Rail droop, reference noise or a weak PDN can appear as intermittent calibration or traffic failure. Review FPGA I/O rails, DRAM rails, termination/reference needs, module power management where applicable, sequencing, decoupling and regulator transient response as one system.

The AMD-Xilinx FPGA power-delivery guide covers the wider FPGA rail tree. For memory, use vendor estimators with actual width, rate and traffic assumptions, then correlate calculations with bench measurements.

Build the BOM around the complete ordering code #

Concrete OPNs make the boundary visible. MT40A1G16KD-062E IT:E identifies more than “16 Gb DDR4”: Micron family, x16 organization, package/speed construction, industrial grade and revision suffix all matter. Other MT40A parts may change organization, footprint or grade while retaining the same headline density.

Apply the same discipline to DDR5. Keep the complete qualified OPN in ERP, AVL and quotations. For modules, record the complete module code, ranks, capacity, speed, ECC/register type and applicable revision.

“Pin compatible” is not “qualified.” Each alternate needs datasheet review, controller-parameter confirmation, a simulation decision and production validation.

Keep engineering and purchasing on the same interface #

Engineering should issue a controlled interface specification, not a generic memory description. Purchasing should return the full candidate OPN, datasheet revision, lifecycle status, traceability evidence, packing condition and availability before substitution approval.

Classify shortage candidates clearly:

• Exact OPN: commercial review, lot and condition confirmation.
• Qualified alternate: confirm the same board, build and rate were covered.
• Engineering candidate: do not release to production until controller, layout and validation impacts are reviewed.

The release packet should include the FPGA and IP versions, schematic/PCB revisions, pin and byte-lane map, controller configuration, approved DRAM list and validation report. This prevents a future cost-down or shortage purchase from silently changing the electrical interface.

Conclusion #

A reliable FPGA DDR4 or DDR5 design begins with the exact FPGA memory resource and controller support, then freezes width, organization, topology, clocks, routing and DRAM OPN as one contract. Calibration is essential evidence, but it is not permission to ignore board or sourcing constraints.

When design files, validation results and RFQs describe the same interface, purchasing can search for supply without turning every alternative into an uncontrolled redesign.

Official references #

• AMD Versal Architecture and Product Data Sheet: Overview (DS950)
• AMD Versal Integrated Memory Controller IP Product Guide (PG313)
• Intel Agilex 7 M-Series EMIF architecture and protocol support
• Intel Agilex 7 M-Series general-purpose I/O and memory-interface overview
• Intel Agilex EMIF DDR4 memory formats and topology parameters
• Intel Agilex 7 M-Series DDR4 discrete-component topology and routing guidance