FPGA Clock Tree Design: Jitter, PLLs and SYSREF

Start with the timing contract, not the clock IC #

An FPGA board that talks to high-speed ADCs or DACs does not have one “clock.” It has a timing contract among the converter sample clock, the FPGA transceiver reference clock, the JESD device or core clock, and—when deterministic latency is required—the SYSREF edge. A clock tree can meet every nominal frequency and still fail because its integrated jitter is too high, its output standard is wrong, or SYSREF is captured too close to a device-clock edge.

The practical design order is therefore:

• Define the converter performance and deterministic-latency requirement.
• Derive every clock frequency and phase relationship from the selected link mode.
• Allocate jitter, skew and setup/hold margin at each receiving pin.
• Select a clock architecture and exact orderable device.
• Validate the programmed state on hardware, at temperature and at the load.

This is a separate system decision from FPGA power delivery. The companion AMD-Xilinx FPGA power-delivery guide covers rail planning and sequencing; this article follows the reference and timing signals after those rails are stable.

Build three budgets before choosing a PLL #

1. Sampling-jitter budget #

For an ADC sampling a sine wave, the theoretical SNR limit caused by total RMS timing jitter is:

SNRjitter = -20 log10(2π × fin × tjitter)

TI's official Clocking Optimization for RF Sampling ADCs uses this relationship and explains that the clock-jitter term becomes more important as analog input frequency rises. At a 1 GHz input, 100 fs RMS total jitter corresponds to an illustrative jitter-only limit of about 64 dB. This is not a clock-chip specification target by itself: converter aperture jitter, oscillator noise, PLL noise, distribution-buffer noise and board coupling combine at the sampling point, normally by root-sum-square for uncorrelated contributors.

Use the integration band required by the converter analysis. A “44 fs” or “54 fs” headline measured over 12 kHz to 20 MHz cannot be compared directly with a number integrated over another band or measured at another output frequency. Phase-noise plots, spurs and the intended carrier frequency belong in the same review as the single RMS figure.

2. Frequency and phase budget #

List each receiver, not just each frequency:

Two 250 MHz outputs are not automatically interchangeable. One may be a low-noise converter clock, another an FPGA core clock with a different receiver standard, and a third may require a defined phase after every synchronization event. Record the receiving pin, standard, termination, divider and delay setting for every output in the clock-tree worksheet.

3. Startup and fault budget #

The timing contract must state what happens after power-on, reference loss, PLL relock and an FPGA reconfiguration. Decide which reference is primary, whether a backup may switch hitlessly, how holdover is used, which lock and loss-of-signal flags software checks, and whether SYSREF is issued once, as an N-shot burst or continuously. A board that only synchronizes after a manual register rewrite does not have a complete startup design.

Why dual-loop clock cleaners are common #

A common high-performance architecture uses PLL1 with an external VCXO to track and clean a system reference, then PLL2 with an integrated VCO to synthesize the high-frequency outputs. The narrow first loop suppresses reference noise outside its bandwidth; the second loop provides frequency multiplication and distribution. The result is not automatically low jitter: VCXO phase noise, both loop filters, PFD rates, VCO choice, divider ratios, supply noise and output-driver mode all shape the final spectrum.

Use a single-loop or distribution-only mode only when the incoming reference and frequency plan justify it. Bypassing a loop can remove one noise contributor, but it also removes that loop's cleaning or translation function. Model the exact configuration in the manufacturer's tool and verify it with the same output frequency, driver mode and integration band used by the converter budget.

SYSREF is an alignment event, not another free-running clock #

In JESD204B/C Subclass 1, SYSREF establishes the deterministic timing boundary shared by the logic device and converter. AMD's current JESD204C guidance states that SYSREF is the master timing reference and must be captured synchronously to the core clock; its permitted period also depends on the IP datapath and line coding. Intel's documented AD9081 JESD204C hardware example likewise recommends that the clock generator supplying the ADC and FPGA device clocks also supply SYSREF to both devices.

Four rules prevent many bring-up failures:

• Derive device clocks and SYSREF from a coherent source. An unrelated FPGA GPIO

pulse is not a deterministic replacement for a clock-chip SYSREF output.

• Choose a SYSREF frequency that satisfies the converter and FPGA IP integer

relationships. Do not copy a frequency from an evaluation board without copying its full JESD mode.

• Place the SYSREF edge inside the valid capture window at every receiver. Use the

clock IC's coarse or fine delay only after accounting for PCB flight time, receiver requirements and temperature margin.

• Prefer one-shot or N-shot operation when the devices support it and continuous

SYSREF is not needed after alignment. Continuous SYSREF can simplify observation but creates another periodic aggressor that must be checked for coupling and spurs.

The AMD JESD204C SYSREF timing documentation and Intel's JESD204C AD9081 hardware setup are useful implementation anchors, but neither replaces the limits for the exact converter, FPGA family, transceiver tile and generated IP version in the design.

Current clock IC choices and exact orderable models #

The table below is a requirements map, not a claim that one device is a drop-in replacement for another. Specifications are from current manufacturer pages and data sheets checked on August 8, 2026.

The lifecycle detail matters. ADI currently marks the original HMC7044 “not recommended for new designs” and lists HMC7044B as the recommended alternative. The B revision is described as improving output phase alignment in temperature and supply-voltage edge cases. That makes HMC7044LP10BETR and HMC7044BLP10BETR distinct BOM identities even though their headline functions, package outline and many specifications appear closely related. Do not silently change the code on a released assembly; review register behavior, qualification evidence and the manufacturer's migration guidance.

AD9528 and LMK04832 are not generic substitutes either. Their output standards, frequency ceilings, delay mechanisms, supply architecture, package footprints, programming flows and SYSREF behavior differ. Select against the receiving pins and synchronization plan first, then compare phase noise under the intended configuration.

A bring-up and validation sequence that exposes real faults #

• Step 1 — freeze the frequency plan. Record converter sample rate, JESD mode, lane

rate, FPGA refclk, core/device clock and SYSREF ratio. Keep the generated FPGA IP configuration with the clock worksheet.

• Step 2 — verify electrical interfaces. Check LVDS, LVPECL, CML, HSTL or LVCMOS

compatibility, common mode, coupling and termination at both ends. “Differential” is not a complete interface specification.

• Step 3 — program and observe lock state. Confirm reference selection, PLL1 and PLL2

lock, VCO calibration and loss-of-signal alarms before releasing JESD resets.

• Step 4 — issue a controlled synchronization event. Capture device clocks and SYSREF

at representative receivers. Adjust documented delay elements to center the valid capture window rather than merely making one board boot.

• Step 5 — repeat deterministic-latency tests. Power-cycle, reset and relink the system

many times; compare latency across channels and devices. Test reference loss and recovery if the product claims that behavior.

• Step 6 — measure the loaded clock. Phase noise at an unloaded evaluation-board SMA is

not the final board result. Check the production driver mode, termination, power supplies and nearby aggressors.

• Step 7 — close temperature and voltage corners. Recheck output phase, capture margin

and lock behavior at the product's operating limits, not only on the bench at room temperature.

Clock outputs deserve their own low-noise supply and return-path review. Isolate switcher harmonics, keep differential pairs referenced and length-controlled, avoid stubs, and follow the exposed-pad and decoupling layout in the current data sheet. The FPGA clock-capable pin assignment and transceiver-bank rules must be frozen before PCB routing begins.

BOM and RFQ controls #

Procurement should receive a clock-tree BOM with full order codes, not family names. For each device, record:

• full manufacturer part number and approved revision;
• package drawing, temperature grade and packing code;
• approved oscillator or VCXO frequency and tolerance;
• evaluation-board or reference configuration used for validation;
• production register image, tool version and checksum;
• lifecycle status and the date it was checked;
• whether any alternate requires FPGA, converter or board requalification.

For HMC7044B, the suffix placement is easy to misread: the required new-design code contains the B immediately after 7044. For LMK04832, NKDT and NKDR distinguish packing quantities; for AD9528, the reel model is AD9528BCPZ-REEL7. An RFQ should preserve these complete codes and state whether engineering has approved any alternate packing or device revision.

Conclusion #

A robust FPGA clock tree is a verified timing system, not a frequency fanout. Budget jitter at the converter input, map every FPGA and converter clock domain, derive SYSREF coherently, and validate deterministic capture across reset, temperature and reference faults. For a new multi-output JESD204B/C design, HMC7044B, AD9528 and LMK04832 are current candidates with materially different interfaces and BOM identities; the older HMC7044 lifecycle status is a specific reason to review rather than copy an established clock circuit unchanged.

Official references #

• Analog Devices HMC7044B product page and current lifecycle position
• Analog Devices HMC7044B Rev. 0 data sheet and ordering guide
• Analog Devices HMC7044 product page and new-design status
• Analog Devices AD9528 product page, lifecycle and order models
• Texas Instruments LMK04832 product page and active status
• Texas Instruments LMK04832 Rev. C data sheet
• Texas Instruments Clocking Optimization for RF Sampling ADCs
• AMD JESD204C PG242 SYSREF timing guidance
• Intel JESD204C AD9081 hardware clock and SYSREF setup