AMD-Xilinx FPGA Power Delivery: Design Guide

Why FPGA power delivery starts with the exact device #

An FPGA power tree cannot be selected from the family name alone. The exact AMD-Xilinx ordering code, package, speed grade, enabled transceivers, memory interface, logic utilization, clock activity and junction-temperature target all change the rail count or current requirement. A small Spartan-7 design and a high-utilization Versal or Zynq UltraScale+ design are both “FPGA power” projects, but they do not present the same regulator, sequencing, transient or thermal problem.

The correct starting point is therefore not a preferred PMIC brand. It is the engineering load case:

• exact FPGA or adaptive SoC part number and package;
• AMD power-estimation output for the intended design configuration;
• required core, auxiliary, I/O, transceiver, processor-system and memory rails;
• rail tolerance, ripple, transient and start-up requirements from the applicable AMD documentation;
• input bus, ambient range, airflow and available PCB area;
• monitoring, telemetry, fault response and functional-safety requirements.

AMD's design methodology says that regulator selection should follow power estimation, rail noise/current requirements, supported rail consolidation and power-distribution-network simulation. It also notes that AMD/Xilinx works with power vendors on documented and tested reference designs. That makes a reference design a strong starting point, but not a substitute for recalculating the load for the exact FPGA implementation.

The power tree has four engineering layers #

The diagram is a LimChip conceptual redraw based on AMD's published power-domain descriptions. It shows why “the FPGA voltage” is not one supply: the programmable logic, auxiliary circuits, I/O banks, transceivers, processor system and external memory create separate electrical jobs.

Input conversion and protection #

The first layer converts the system bus into an intermediate voltage and protects the downstream rails. A 5 V development platform, a 12 V PCIe card and a 12 V or 24 V automotive controller lead to different choices. Input range, surge, reverse polarity, inrush, hot-swap behavior and EMI must be defined before the point-of-load regulators are selected.

This is one reason an automotive MPS reference design based on a wide-input MPQ8886 architecture must not be presented as a universal drop-in solution for every Zynq UltraScale+ board. It solves a specific input, temperature and EMC problem.

High-current core rails #

VCCINT and related core rails usually create the hardest transient and thermal challenge. Current depends heavily on logic utilization, clocking and workload. Higher-performance devices can require multiphase controllers, parallel modules or digitally managed power stages. The design target is not merely the rated DC current: the regulator, compensation, output network and layout must keep the rail inside the device tolerance during fast load steps.

Auxiliary, I/O and transceiver rails #

VCCAUX, VCCO and transceiver analog rails may draw less current, but they can impose tighter noise, rail-isolation or sequencing considerations. I/O voltage follows the selected standards and bank plan. Transceiver rails must be checked against the exact device family and enabled GT resources. Combining rails can reduce component count only where AMD documentation explicitly permits it for the selected device and configuration.

DDR and peripheral rails #

Zynq and other processor-rich platforms often add DDR supply and termination, reference voltages, clocking, storage and peripheral rails. A PMIC that covers the FPGA itself may still require a separate DDR termination regulator such as TPS51200 or MPQ20073, plus load switches, supervisors or sequencers.

Evidence matters more than a long compatible-parts list #

A technically plausible regulator is not automatically an AMD-approved solution. LimChip uses evidence labels so engineers and buyers can distinguish a tested platform from a general component suggestion.

The purchasing implication is direct: a quote should preserve the full ordering code and the reference-design context. Replacing a regulator with a part that has the same nominal voltage and current can change compensation, pin programming, telemetry, sequencing or thermal performance.

Four vendor paths, with different strengths #

This coverage map summarizes the named families visible in the official resources cited below. A filled path means that the vendor publishes a relevant design or family resource; it does not mean that every device, package and workload within that family is covered.

Analog Devices: the broadest visible family map #

ADI maintains a dedicated AMD-Xilinx FPGA power-delivery library covering legacy 7-series platforms through UltraScale, UltraScale+ and Versal designs. The library explicitly separates verified and non-hardware-verified entries. It includes named boards and device targets such as ZC702/ZC706, KC705, KCU105, Virtex platforms, Versal AI Core XCVC1902 and Versal HBM concepts.

ADI's AMD-Xilinx library is especially useful for tracing a power tree back to a named FPGA family or development platform. The fully tested ZedBoard power design gives a concrete 7-series example: two MAX15021 dual-output bucks supply VCCINT, DDR and I/O rails; MAX15053 supplies VCCAUX; MAX1983 supplies VCCADC; MAX6037A provides the 1.25 V XADC reference; MAX1510 handles DDR termination; and MAX8686 creates the 5 V intermediate rail when it is needed. This is valuable hardware evidence, but it is also a mature platform BOM. Lifecycle and recommended replacements must be checked before using those parts in a new long-life product.

Renesas: integrated PMIC designs for 7-series devices #

Renesas publishes three reference boards around the ISL91211 PMIC family for Artix-7, Spartan-7 and Zynq-7000. The official material identifies the supporting devices and rail roles:

• Artix-7: ISL91211AIK, ISL91211BIK, ISL80030 and ISL21010DFH312;
• Spartan-7: ISL91211BIK and ISL80030;
• Zynq-7000: ISL91211AIK, ISL9123 and two ISL80030 converters.

Renesas describes these boards as tested, complete reference solutions and provides user guides, schematics, BOMs and PCB files. Their value is integration and a documented rail mapping. Their boundary is equally important: this evidence names 7-series families, not every newer UltraScale+ or Versal device.

Texas Instruments: scalable reference boards and explicit rail tables #

TI's TIDA-050000 targets Artix-7, Spartan-7 and Zynq-7000. Its published design uses devices including TPS65023/TPS65023B, TPS568215, TPS62067 and the optional TPS51200 DDR termination regulator. TI documents configurable variants, rail voltages and current limits rather than presenting one fixed BOM as universal.

For Zynq UltraScale+ MPSoCs, TIDA-01480 is documented for ZU2CG through ZU5EV devices in the stated package/configuration range. Its scalable architecture includes TPS65023, TPS568215, TPS56C215, TPS62067, TPS51200 and TPS22920 roles depending on the selected variant.

TIDA-050000 and TIDA-01480 are strong prototyping references because the supported device range and rail table are explicit. They are not evidence for an unlisted device such as a larger ZU19EG without a fresh requirements review.

Monolithic Power Systems: modules and automotive Zynq UltraScale+ #

MPS presents two useful directions. For high-density FPGA rails, it highlights the MPM3695-10/MPM3695-25 module family and MPM3632C, including parallel operation for higher core current. For automotive Zynq UltraScale+, MPS publishes a scalable reference design for ZU2CG through ZU5EG using MPQ8886-0000-AEC1, MPQ4433-AEC1, MPQ2166A-AEC1, MPQ8904-AEC1, MPQ20051-AEC1 and MPQ20073-AEC1.

The MPS automotive reference document includes schematics, BOM, efficiency, steady-state, sequencing, thermal and EMC test material. It is valuable evidence for an automotive-style wide-input design, but the stated device range and test conditions must remain attached to any claim.

Match the FPGA family before comparing vendors #

As the platform moves from cost-optimized 7-series logic toward processor-rich Zynq UltraScale+ and Versal devices, the design problem shifts from a compact multi-rail PMIC toward higher core current, more domains, telemetry and tighter system-level validation. This is a design-complexity view, not a power-consumption ranking: actual power still depends on the exact device and workload.

The following matrix is a navigation aid, not a claim that every listed vendor has an equivalent verified design for every device.

An example such as XC7Z020-2CLG400I is useful for SEO and procurement only when the suffix remains intact. CLG400 defines a different package context from another XC7Z020 ordering code; the power estimate and board constraints must follow the exact design. The same rule applies to temperature grades and automotive-qualified regulator suffixes.

A practical engineering selection workflow #

Freeze the device and workload assumptions #

Record the full FPGA ordering code, memory devices, interfaces, transceiver count, clocks, utilization and operating range. Generate the power estimate using the intended workload assumptions and retain the file with the design release.

Build a rail-by-rail requirements table #

For every rail, record nominal voltage, tolerance, estimated static/dynamic current, transient target, ripple/noise limit, start-up order, discharge requirement and monitoring need. Keep “may be consolidated” separate from “will be consolidated.”

Find the closest evidence-backed design #

Match the FPGA family, device range, input bus and application class. A reference for ZU2CG-ZU5EV is stronger evidence for those devices than a generic 12 A regulator suggestion, but it still requires comparison against the new XPE result and board conditions.

Recalculate current, compensation and thermals #

Check phase count, inductor or integrated-module limits, switching frequency, thermal derating, copper area and airflow. Validate transient behavior and PDN impedance. For high-current designs, include telemetry or current measurement points so laboratory results can be compared with the estimate.

Release a controlled sourcing BOM #

The approved BOM should include manufacturer, complete ordering code, package, temperature/qualification grade, programmed option where applicable, lifecycle status and allowed alternates. A PMIC with OTP or multiple configuration suffixes must not be purchased from a shortened generic part number.

RFQ and incoming-inspection checklist #

• Provide the exact AMD-Xilinx FPGA and every power-device ordering code, not only the base family.
• State whether the BOM comes from a vendor reference design, evaluation board or a custom engineering design.
• Confirm input voltage, output rail/current role and required automotive or industrial grade for each regulator.
• Ask for lifecycle status, date code, lot consistency, packaging condition and traceability before order release.
• Treat programmed PMIC variants, automotive suffixes and package options as non-interchangeable until engineering approves them.
• For mature reference boards, check whether the original regulator is still recommended for new designs and whether a footprint-compatible successor exists.
• Re-run power and thermal validation whenever the FPGA utilization, memory population or transceiver configuration changes.

What this series will cover next #

The next articles will examine ADI, Renesas, MPS and TI separately. Each vendor article will map named FPGA families and development boards to specific power ICs, separate verified hardware from proposed designs, and identify sourcing details that can invalidate an apparently similar replacement. A final article will compare evaluation-board BOM evidence and show how to turn a reference design into a controlled production RFQ.

The purpose is not to crown one universal winner. FPGA power is a requirements-matching problem. The best solution is the one with the right evidence, rail performance, thermal margin, lifecycle and supply-chain fit for the exact AMD-Xilinx device and workload.

For a design-specific review, send the FPGA ordering code, XPE output, input bus, production quantity and required qualification grade. Those five items are more useful than a generic request for an “FPGA power solution.”

Official references #

• AMD UltraFast Design Methodology: Power Distribution System
• AMD UltraScale+ Power Domains
• Analog Devices AMD-Xilinx FPGA Power Delivery Solutions
• Analog Devices ZedBoard Power Reference Design
• Renesas PMIC Reference Designs for Xilinx FPGAs and SoCs
• Texas Instruments TIDA-050000 for Artix-7, Spartan-7 and Zynq-7000
• Texas Instruments TIDA-01480 for Zynq UltraScale+
• MPS High-Performance FPGA Power Supply Solutions
• MPS Scalable Automotive Power Supply for Xilinx Zynq UltraScale+