Altera Arria V GX Ordering Codes Guide

Altera's current Arria V GX ordering figure uses 5AGXFB5H4F35I3N as its sample. Read it as 5A | GX | F | B5 | H | 4 | F | 35 | I | 3 | N: family, variant, embedded hard-IP option, member, transceiver count, transceiver speed, package type, package code, temperature, FPGA fabric speed and RoHS suffix.

Every field belongs in an RFQ. A shortened request such as 5AGXFB5 omits the transceiver population, two speed grades, package footprint, temperature range and material suffix.

Open the full-size Arria V GX ordering diagram and zoom.

Decode 5AGXFB5H4F35I3N field by field #

Member, hard-IP and transceiver fields are functional choices #

The F before B5 is not the package letter. It is the embedded-hard-IP option. The later F before 35 is the FineLine BGA package type. Confusing those two identical letters is an easy way to request the wrong device.

The hard-IP field changes PCIe and hard memory-controller resources: B has neither hard PCIe nor hard memory controllers, M provides one hard PCIe block and two hard memory controllers, and F provides the maximum shown GX combination. The member code then selects the density tier, while D, G, H or K selects the transceiver population. A replacement must preserve all three functions required by the design.

Package code defines the PCB boundary #

For the GX figure, F27, F31, F35 and F40 correspond to 672, 896, 1,152 and 1,517 balls. They are different footprints. A move from F35 to F31 is not pin-to-pin simply because both parts are Arria V GX devices.

The package code must also be checked against the package plan for the exact member and hard-IP combination. A code listed somewhere in the family does not prove that every GX member is orderable in that package.

Temperature and speed replacement logic #

When the original C-temperature OPN is unavailable, an otherwise identical I-temperature OPN can be a candidate because I extends operation from −40°C to 100°C, compared with 0°C to 85°C for C. That direction can provide wider environmental coverage, but it is not automatic approval. Confirm the exact OPN exists, check the timing model, power, qualification record and programming flow, and expect the industrial device may cost more.

The reverse direction is not equivalent: a C device does not satisfy an industrial temperature requirement. The two speed fields also need separate checks. Transceiver grade 4 versus 6 changes serial capability, while FPGA fabric grade 3 versus 4, 5 or 6 changes core timing. A faster grade can be an engineering alternate candidate for a slower grade only after timing, power and tool support are reviewed for the exact target.

Pin-to-pin and vertical-migration boundaries #

Altera's current Arria V overview explicitly shows no vertical migration capability between different variants. GX-to-GT, GX-to-GZ and GX-to-SoC changes therefore cannot be treated as pin-compatible substitutions from a shared Arria V name.

Within GX, the official package and migration tables remain the authority. Matching F35 is necessary for an F35 candidate but not sufficient: the planned migration path must support both members, and the board must accommodate every changed power, transceiver and user-I/O assignment. Recompile the project for the candidate device and review pin, timing, power and configuration reports before purchasing replacement stock.

Procurement checklist #

1. Copy the complete OPN from the released BOM, including the final N, G or P suffix. 2. Match the 5A family, GX variant, embedded-hard-IP field and member code. 3. Preserve the required transceiver count and check the transceiver speed grade separately. 4. Match package type and package code; verify ball count, body size and PCB land pattern. 5. Treat wider temperature coverage or faster speed as an engineering candidate, not automatic approval. 6. Confirm the current package plan and vertical-migration table for both exact devices. 7. Recompile and review pin assignments, timing, power, configuration output and qualification. 8. Confirm lifecycle, traceability, date code, packing medium, quantity, lead time and price before release.

Conclusion #

An Arria V GX orderable code is complete only when both speed grades, hard-IP and transceiver choices, package, temperature and RoHS suffix are present. Same-family stock can still be electrically or mechanically unsuitable. The safest shortage substitution keeps the complete functional and package identity unchanged, then uses the official migration table and a project-specific Quartus review to prove the candidate.

Official references #

• Arria V Device Overview
• Arria V GX available options and ordering information
• Arria V I/O vertical migration guidance
• Arria V Device Overview revision history
• Arria V GX product overview