Altera Cyclone V SE Ordering Codes Guide

Cyclone V SE is a SoC FPGA, so its ordering code includes processor-core and power-option fields that do not appear in the Cyclone V E decoder. Intel's official Figure 4 example 5CSEMA6F31C6SLN reads as 5C | SE | M | A6 | F | 31 | C | 6 | S | L | N.

That sequence identifies Cyclone V, the SE SoC variant, M hard-IP option, A6 member, FineLine BGA, 896 pins, commercial temperature, FPGA fabric speed grade 6, single-core processor option, low-power option and lead-free packaging. The full OPN belongs on the BOM and RFQ; 5CSEA6 does not identify the HPS configuration or footprint.

Open the full-size Cyclone V SE ordering diagram and zoom.

Decode 5CSEMA6F31C6SLN field by field #

Hard IP, density and processor fields are separate #

Cyclone V SE member codes A2, A4, A5 and A6 represent approximately 25K, 40K, 85K and 110K logic elements. The preceding hard-IP character is not part of the density. B means no hard PCIe or hard memory controller, while M means no hard PCIe and one hard memory controller.

The processor-core option appears after the FPGA fabric speed grade. A blank field identifies the dual-core Cortex-A9 configuration; S identifies a single-core device. A candidate with the same A6 density and F31 package but a different processor-core field is not a transparent substitute because software, boot, performance and HPS resource assumptions may change.

Package and footprint boundaries #

The official SE decoder lists F31 as the 896-pin FineLine BGA option. Ultra FineLine BGA uses U19 and U23 for 484 and 672 pins. These are three distinct physical choices; changing F31 to U23 is not pin-to-pin even though the smaller package may expose sufficient logical resources for another design.

Altera's current product table shows that package availability varies by density. A2 and A4 are listed in U19 and U23, while A5 and A6 also have F31 options. GPIO and HPS I/O counts differ by package. Confirm the exact orderable-product record, package drawing, pin file and package plan before approving an alternate.

Temperature, speed, power and suffixes #

The official fields are C for commercial 0°C to 85°C, I for industrial −40°C to 100°C and A for automotive −40°C to 125°C junction temperature. FPGA fabric grades are 6, 7 and 8, with 6 fastest.

The L power option is available on selected Cyclone V SE and SX industrial-grade devices. The official overview states a 30% static-power reduction for 25K and 40K devices and 20% for 85K and 110K devices. Current product records show examples such as 5CSEBA5U19I7LN. Do not insert L into an arbitrary commercial or automotive OPN; check the exact ordering table.

N identifies lead-free packaging. ES identifies an engineering sample and is not a production substitute. SC identifies internal-scrubbing support on selected devices and must be confirmed for the exact OPN.

Replacement screening and pin-to-pin limits #

For first-pass alternate screening, preserve 5CSE, the B/M hard-IP field, processor-core option and complete package code. Then compare member, temperature, fabric speed, power option and suffix.

For example, 5CSEBA5U19C8N and 5CSEBA5U19I7N retain the SE variant, B hard-IP option, A5 member, dual-core configuration and U19 footprint. The industrial part widens the low-temperature range and grade 7 is faster than grade 8, so it can enter shortage-alternate review. It may cost more and still requires timing, power, software, qualification and customer approval.

Changing U19 to U23 or F31 is not pin-to-pin. Changing B to M changes the hard memory-controller resource. Adding S changes the processor configuration, and adding L changes the power option and availability boundary. Altera's vertical-migration guidance requires checking migration compatibility in Quartus Prime Pin Planner; common package naming alone does not prove compatible power, configuration, dedicated or HPS pins.

Reject a claimed drop-in alternate when:

• the SE variant or B/M hard-IP field changes without design review;
• the complete package field changes;
• the processor-core option changes;
• L, ES or SC appears unexpectedly;
• temperature or speed grade is outside the qualified build;
• Quartus Pin Migration View reports incompatible assignments;
• HPS DDR, boot, clock, power, configuration or dedicated-pin requirements differ.

Procurement checklist #

1. Copy the complete OPN from the released BOM. 2. Confirm 5C family, SE variant and B/M hard-IP field. 3. Match A2–A6 member resources. 4. Treat package letter and package number as one footprint field. 5. Confirm C, I or A temperature and fabric grade 6, 7 or 8. 6. Confirm blank or S processor-core option explicitly. 7. Confirm standard or L power option from an official orderable record. 8. Preserve N material status and reject ES unless authorized. 9. Check the package plan, pin file and Quartus Pin Migration View. 10. Revalidate HPS software, boot, DDR, timing and power assumptions.

Conclusion #

Cyclone V SE comparisons must preserve more than density and package. In 5CSEMA6F31C6SLN, M selects the hard memory-controller option, S selects single-core operation and L selects low power. A wider temperature range or faster fabric grade may help during shortages, but a different package, hard-IP field, processor option or power option crosses the drop-in boundary.

Official references #

• Altera Cyclone V Device Overview
• Intel-hosted Cyclone V Device Overview PDF, Figure 4
• Altera Cyclone V SE product and ordering table
• Altera Cyclone V SE A5 U19 ordering records
• Altera Cyclone V I/O vertical migration guidance
• Altera Cyclone V device datasheet