Altera Arria 10 Ordering Codes and Replacement Guide

An Arria 10 family name such as 10AX027 identifies the general device, but it is not a complete purchasing description. The full orderable part number also defines the transceiver option and PMA speed, package, temperature grade, core speed, power option and compliance suffix. Those fields determine whether a proposed device fits the released PCB and qualification requirements.

This guide uses 10AX027H4F34I3SG as a procurement example. The diagram first preserves Altera's official syntax example, 10AX066K2F35I2SGES, so every connector—including the optional `ES` suffix—retains the topology published in the current Arria 10 Device Overview. The field meanings then apply to the procurement example below.

Decode 10AX027H4F34I3SG field by field #

The code can be separated as 10A | X | 027 | H | 4 | F | 34 | I | 3 | S | G.

The split is important because the two numbers around the package do different jobs. In this example, 4 is associated with transceiver performance, 34 identifies the package code, and 3 is the core speed grade. Treating every number as a density or pin count can produce the wrong RFQ.

GX, GT and SX are different device variants #

Arria 10 includes more than one device variant. GX targets transceiver-equipped FPGA applications, GT extends the transceiver-performance range for demanding links, and SX combines FPGA fabric with a hard processor system. Their orderable codes therefore do not represent interchangeable versions of one board footprint.

Before comparing price or availability, establish which architectural features the design uses:

• hard processor system and boot flow;
• number and placement of transceiver channels;
• required PMA data rate;
• PCI Express and other hard IP;
• external-memory interfaces;
• package-specific GPIO and transceiver availability.

A change from 10AX to 10AS is a platform decision, not a suffix upgrade. It affects hardware and software architecture and should be treated as a redesign.

Package code is the first physical compatibility gate #

The F34 portion does not merely mean “BGA.” It identifies a specific FineLine BGA package option. A candidate with another F-code may have a different ball count, body size, pitch, pinout or mix of GPIO and transceiver pins.

Altera publishes package plans and an I/O vertical-migration table. Use those documents to identify possible migration paths, but do not turn a vertical-migration indication into automatic pin compatibility. The released design must still be compiled for the candidate device, and the PCB assignments, power pins and configuration requirements must be checked.

Use these three labels during sourcing:

Temperature, PMA speed and core speed are separate approvals #

Arria 10 orderable codes keep operating temperature, PMA speed and core speed as distinct fields. A candidate can improve one field while changing another.

For example, an industrial-temperature candidate may cover a wider environmental range than a commercial device, but that does not prove that its PMA and core speed combination is approved for the design. Conversely, a faster transceiver grade does not automatically guarantee that the FPGA core timing, power or qualification file is unchanged.

For every proposed grade change:

1. confirm that the exact combination is orderable; 2. select the candidate in Quartus Prime; 3. recompile the complete project; 4. review timing, transceiver settings and power estimates; 5. verify the qualification and environmental requirements; 6. document the commercial impact separately.

“Faster” or “wider temperature” means candidate, not automatically approved substitute.

Power option and suffix checks #

The power-option field affects how the device is represented in the power and ordering documentation. It must be matched to the approved power architecture and tool settings. Do not omit it from the RFQ or assume that two OPNs differing only in that field are interchangeable.

The final compliance suffix is also part of the orderable code. Keep it visible in quotations, purchase orders, labels and incoming inspection. Product top marking additionally contains manufacturing and traceability information; Altera's Arria 10 product-marking guide explains the marking layout and date-code presentation.

Controlled Arria 10 alternate-screening workflow #

When the approved OPN is unavailable, screen candidates in this order:

1. Preserve the full approved OPN. Record every field before asking for alternates. 2. Match the variant and density. Keep GX/GT/SX and the density member unchanged unless engineering accepts an architectural change. 3. Match the package. Check package code, package drawing, pinout and official migration table. 4. Check the transceiver option and PMA grade. Confirm channel placement, count, protocol and line-rate requirements. 5. Check temperature, core speed and power option. Review each field independently. 6. Compile and verify. Re-run fitting, timing, transceiver and power analysis in Quartus Prime. 7. Inspect the material. Confirm full marking, lot/date code, moisture-barrier packaging and traceability. 8. Compare commercial terms last. Price, MOQ and lead time matter only after the candidate passes technical screening.

RFQ checklist #

Conclusion #

An Arria 10 purchase decision should end with the complete orderable code, not the short density name. In 10AX027H4F34I3SG, every field after 10AX027 narrows the transceiver, package, environmental, performance, power and compliance configuration.

The safest shortage candidate normally preserves the device variant, density and package first. Grade changes can then be evaluated as controlled upgrades, but only after the exact OPN is confirmed as orderable and the design passes pinout, Quartus, timing, transceiver, power and qualification checks.

Official references #

• Arria 10 Device Overview
• Arria 10 Available Options and Sample Ordering Code
• Arria 10 I/O Vertical Migration
• Arria 10 Core Fabric and General Purpose I/Os Handbook
• Product Marking Information for Arria 10 Devices