Multiphase PWM Controllers and Smart Power Stages

Select the controller and power stage as one system #

A high-current accelerator core rail is not defined by phase count alone. The multiphase PWM controller, smart power stages, inductors, output network, remote-sense point, processor voltage interface, PMBus configuration and cooling path form one regulated system. A controller that can drive twelve or twenty phases is only a candidate until its interface, control law, telemetry scaling and fault behavior have been matched to the selected stage and the processor's published rail requirements.

This is the decision boundary for AI accelerator, ASIC and large-FPGA boards: freeze the load envelope and control contract first; then choose a documented controller-and-stage ecosystem; finally prove transient, thermal and fault margin on the destination PCB. Do not infer the power BOM of an unpublished NVIDIA, AMD or other accelerator from a controller vendor's general application list.

The preceding accelerator board power-tree guide sets the boundary between the 48/54 V entry, intermediate bus, compute core and HBM rails. This article starts at the local high-current rail and explains how to release its controller, power stages and configuration as one BOM unit.

Freeze the electrical contract before comparing parts #

Begin with the processor or FPGA power specification and a dated workload estimate. Record nominal voltage, allowed static and dynamic error, load line, maximum continuous current, peak current and duration, load-step amplitude and edge rate, startup and shutdown behavior, pre-bias rules, voltage-identification interface, fault response and telemetry requirements. The current estimate must include the actual device, package, clocks, utilization and operating mode.

Then define the board constraints: input range at the regulator, available phase area around the load, copper and via budget, airflow or cold-plate boundary, permitted component height, output-capacitor placement and the true remote-sense location. These constraints decide whether more phases improve margin or merely add switching loss and routing congestion.

Use a slower, lower-power operating point for first bring-up, but do not let it become the release criterion. A rail that survives configuration traffic may still fail at the fastest workload transition or at the hottest phase under a cold-plate edge.

Choose the control interface before the phase count #

The processor-side voltage interface is not interchangeable with PMBus. AVSBus, SVID, SVI and PWM-VID communicate operating-voltage intent according to different platform contracts. PMBus or I2C is normally the management plane for configuration, telemetry and faults. A controller can support more than one interface, but firmware, register maps and host behavior remain device-specific.

Phase count follows current, transient, efficiency and thermal analysis. A first estimate divides expected current by a conservative per-phase current, then adds margin for imbalance and thermal derating. That arithmetic is not a design approval: switching frequency, inductor value, coupled or TLVR magnetics, phase shedding, control law and output capacitance change both current ripple and transient response.

The current public portfolios illustrate why the interface decision comes first:

These are selection examples, not approved cross-vendor pairings and not a recommendation for a named accelerator. A public evaluation module or reference design proves only its documented board, components and test conditions.

Pair the smart stage by signals, scaling and fault semantics #

A smart power stage integrates the high-side MOSFET, low-side MOSFET and gate driver, then adds some combination of current sense, temperature sense, enable and fault reporting. The familiar 3.3 V tri-state PWM input does not make two stages interchangeable. The controller expects specific current-sense gain and offset, temperature transfer function, bias rails, fault encoding, startup state and switching behavior.

Current examples show the differences that must stay visible in the BOM:

The active Renesas page is also a useful lifecycle warning: the ISL99390HRZ-TR5935 option is listed as last-time-buy while the FRZ variants are active. A quotation that removes one letter from the suffix can therefore change PWM compatibility or lifecycle status.

Treat a stage change as a control-loop and thermal change. At minimum, review pinout, land pattern, current-sense scaling, temperature scaling, fault table, dead time, switching-frequency range, bootstrap behavior, enable thresholds, reverse-current behavior, package thermal impedance, MSL and packing code.

Make telemetry useful before trusting it #

Telemetry is valuable only after it is calibrated and tied to the same sense point used for regulation. Establish the current-sense gain and offset per phase, temperature transfer function, controller coefficients, PMBus data format, sampling cadence and fault-latch behavior. Compare reported voltage, current and temperature with independent bench instruments across load and temperature.

Per-phase current readback is a diagnostic, not just a dashboard number. It can reveal an open PWM connection, inductor variation, asymmetric copper, poor thermal contact or a stage approaching current limit. A balanced total current reading can hide one hot phase, so archive individual phase telemetry whenever the controller exposes it.

Define who owns the NVM image. Store the controller OPN, configuration file, checksum, tool version, PMBus address, write-protection state and production programming station in the release packet. A blank controller and a programmed controller with the same package marking are not equivalent production items.

Validate the load step as an energy path #

When load current rises, the output capacitors provide the first energy while the controller detects error and the inductors ramp phase current. The allowed voltage excursion is therefore shared among control delay, inductor slew, capacitor capacitance, ESR/ESL, plane impedance, load line and the remote-sense path. Adding capacitance can help, but it cannot repair an unstable loop, a misplaced sense point or an input plane that collapses.

On load release, excess inductor energy creates overshoot. Diode braking, phase turn-off behavior, active voltage positioning and any negative-current capability must be evaluated against the processor's absolute and dynamic limits. Test the real slew rate; an electronic load with slow leads can make a weak design look good.

TI's public PMP21887 is a useful evidence boundary: it documents a 12-phase 0.85 V reference for datacenter accelerator and networking ASIC core rails at 360 A continuous and 600 A peak. Those numbers describe that reference design; they are not ratings for every TPS536C7 board or permission to copy its output network without the processor's own transient specification.

Run electrical, thermal and fault tests separately #

A release test needs more than one successful load step.

1. Static regulation: sweep input, load and commanded voltage; compare the remote-sense voltage, load-line target and independent instrumentation.

2. Dynamic margin: test the specified load-step amplitude, slew rate, repetition and release event at cold, room and hot conditions. Capture the input plane, output at the sense point and output at the load simultaneously.

3. Phase balance: record every phase current and stage temperature at steady state and during transitions. Investigate systematic outliers rather than averaging them away.

4. Thermal boundary: test the actual heatsink, airflow or cold plate, TIM, board copper and neighboring heat sources. A stage's headline current is not the allowable current in an unverified mechanical stack.

5. Fault behavior: exercise UVLO, overcurrent, short circuit, stage fault, overtemperature, loss of sense and communication timeout where safely supported. Confirm whether each event retries, hiccups, latches off or remains logged.

6. Configuration integrity: power-cycle, brown out and reset the board; verify that the intended NVM image, limits, phase allocation and telemetry coefficients return every time.

The pass/fail table should use the processor's permitted voltage window and the component vendors' documented operating limits. A visually smooth trace is not a limit.

Release a controller-stage BOM group, not isolated line items #

The purchasing package should keep the electrical system together:

Do not accept “same 90 A SPS,” “pin compatible controller” or “same PMBus” as a substitution rationale. An alternate can require new coefficients, compensation, layout, thermal model, firmware and fault validation even when it fits the same footprint.

The related TDA22590 sourcing guide and ISL99390FRZ-TR5935 demand guide cover exact-stage procurement checks. This system guide explains why those stages must remain tied to their controller, configuration and validation evidence.

Conclusion #

The right multiphase regulator is the one whose processor interface, phase architecture, smart-stage feedback, output network, firmware image and thermal path have been validated together. Maximum phase count and per-stage current are useful filters, but they do not establish compatibility or margin.

Freeze the complete controller-stage contract in engineering, preserve it in the AVL and RFQ, and require a controlled requalification whenever a controller, stage suffix, inductor, capacitor set or programmed image changes.

Official references #

• TI TPS536C7 active product page and datasheet
• TI TPS536C7EVM-051 controller and CSD95410 smart-stage evaluation module
• TI PMP21887 360 A continuous / 600 A peak ASIC core reference design
• Renesas ISL68137 active seven-phase AVSBus controller
• Renesas ISL99390R5935 and ISL99390BR5935 smart power stage product page
• Infineon XDPE19284C-0000 active dual-loop eight-phase controller
• Infineon TDA22590 active 90 A integrated smart power stage
• MPS MP2880 active 20-phase digital controller
• MPS MP86957 active 70 A Intelli-Phase stage