HBM3E Power Delivery: Rails, PDN and Validation

HBM3E power is a package contract, not a generic memory rail #

HBM3E raises a deceptively simple question: what regulator powers the memory? The useful answer starts one level higher. HBM3E is integrated beside an accelerator on an interposer or advanced package, so its rail names, voltage limits, current profiles, sequence, sensing points, decoupling model and thermal limits belong to that exact accelerator package and board release. A memory vendor's bandwidth or performance-per-watt claim does not disclose this power contract.

That boundary matters now because current HBM3E products span materially different stack constructions. Micron's current HBM3E material lists 24 GB 8-high and 36 GB 12-high products at more than 9.2 Gb/s and more than 1.2 TB/s per stack. Samsung lists 24 GB/36 GB, 8-high/12-high HBM3E at up to 9.2 Gb/s and 1,180 GB/s, while SK hynix announced volume production of a 36 GB 12-layer product at 9.6 Gb/s. Those are valuable memory facts, but none authorizes an engineer to copy a rail voltage, transient budget or regulator BOM from another accelerator.

The design decision is therefore to freeze a package-specific HBM power specification before selecting regulators. Procurement must then preserve the regulator configuration, output network, board stack-up, cooling boundary and test evidence with the accelerator OPN. This guide explains that release method without inferring an unpublished NVIDIA, AMD or other accelerator BOM.

The preceding accelerator board power-tree guide separates the 48/54 V input, intermediate bus, compute core and memory domains. This article starts at the HBM regulator outputs and defines what must be controlled between those outputs and the memory inside the package.

Freeze every rail from the platform document #

Do not begin with a label such as “HBM VDD.” Begin with the accelerator vendor's current power specification, package pin map, power-estimation output and board design guide. Record every memory-related rail even when several rails share a nominal voltage. Separate names can indicate different loads, tolerances, sequence dependencies, noise limits or sense points.

AMD's current Versal HBM documentation provides a public example of why rail identity matters. Its HBM2e device exposes VCC_HBM for the memory, VCCO_HBM for HBM I/O, VCCAUX_HBM for auxiliary functions and VCCINT_IO_HBM for the controller interface. The same data sheet assigns different recommended voltages to those rails and ties VCCINT_IO_HBM to the device's operating-voltage mode. These names and values are valid for the documented Versal HBM device; they are not a generic HBM3E specification.

The same discipline applies to unused resources. AMD's June 2026 Versal PCB guide says its HBM2e stack rails should remain connected even when a stack is not intended for use. Treat that as a device-specific instruction, not a rule for every HBM3E package; the lesson is to check unused-domain requirements rather than assume an inactive stack may be left unpowered.

Convert the workload into a target impedance #

A regulator current rating is only the first filter. The PDN must keep the voltage at the package-defined observation point inside its DC and AC limits while HBM traffic changes. Obtain the accelerator vendor's current estimate for the exact device, HBM population, memory rate, workload, ambient and thermal state. Archive the tool version and input vector; “maximum HBM bandwidth” is not a reproducible current profile.

Split the voltage budget before calculating impedance. Regulator accuracy, load-line or set-point error, plane IR drop and dynamic ripple cannot all spend the same tolerance. After allocating the AC ripple budget, use the familiar relationship:

> Target PDN impedance = allowed AC voltage excursion / current step

AMD's 2026 Versal PCB guide uses this method and recommends full board-level PDN simulation. It also gives a separate plane-resistance check: the permitted DC drop divided by expected rail current sets an initial maximum resistance. That distinction is important. More MLCCs can reduce impedance over part of the frequency range, but they cannot repair a narrow neck, excessive via resistance or a sense line that observes the wrong node.

Build the impedance model through the complete path:

1. Regulator output impedance and control-loop response. 2. Bulk and mid-frequency capacitance, including ESR and mounting inductance. 3. PCB planes, neck-downs, vias and connector or module transitions. 4. Land-side capacitors and package mounting inductance. 5. Package/interposer model supplied for the accelerator release. 6. On-package or on-die capacitance where the vendor model includes it.

Use capacitor values at operating voltage and temperature, not nameplate capacitance. Sweep component tolerances and look for anti-resonance peaks rather than approving only a smooth nominal curve.

Put remote sense at the specified load plane #

Remote sense compensates predictable DC loss; it does not remove plane impedance or package inductance. Route the sense pair to the exact package or land-side locations defined by the accelerator vendor, keep it away from switch nodes and phase-current paths, and follow the regulator vendor's filtering and stability guidance. Sensing at a convenient capacitor near the regulator can make the controller report a healthy voltage while the HBM package sees droop.

Do not merge HBM-related rails only because they share a nominal set point. Before consolidation, confirm allowed common sequencing, combined ripple, cross-load behavior, fault containment, current telemetry, sense topology and power-state behavior. A merged rail can couple a compute transient into memory or turn one fault into a package-wide reset.

The public MPS Versal HBM reference design is useful as an evidence boundary. AMD currently classifies the MPS Versal HBM designs as paper/concept references, not hardware-verified reference designs. MPS's size-optimized full-power page lists one MPM3695-100-0001 high-current module plus multiple MPM3683-10, MPM3650C, MPM3606A, MPM3683-7, MPM3632C and MPM3620 modules and an MPQ7962-0010 monitor. That page demonstrates multi-rail partitioning for named Versal HBM devices; it does not qualify those parts for HBM3E.

For an exact current catalog example, MPS lists MPM3695GBH-100-0001 as Active. The module supports a 0.5 V to 3.3 V output range, 100 A continuous output up to 1.8 V, remote sense, PMBus telemetry and a 15 mm × 30 mm BGA. Those capabilities make it a candidate only after the destination rail's voltage, transient, mechanical and thermal requirements are known. Its configuration code, not just the MPM3695-100 family name, belongs in the BOM.

Validate electrical and thermal behavior on different clocks #

HBM power failures do not all appear at the same timescale. Package capacitance responds first, board MLCCs and the regulator loop follow, and temperature rises over a much longer interval. A short synthetic pulse can pass the voltage test while sustained bandwidth heats the stack until refresh, error rate or throttling behavior changes. Conversely, a thermal soak can miss a nanosecond-to-microsecond droop that corrupts traffic immediately.

Use a synchronized release test with three evidence channels:

• Electrical: measure regulator input, regulator output and the specified

package/load-plane point during the documented HBM traffic transition. Record peak droop, overshoot, ringing frequency, settling and rail-to-rail coupling.

• Control: capture enable, power-good, telemetry, fault and reset state. Make

sure PMBus sample rate and averaging are not mistaken for oscilloscope evidence.

• Thermal: log HBM stack, package, regulator/module, inductor and relevant

cold-plate or coolant temperatures through steady bandwidth and recovery.

Micron specifies a 0°C to 105°C operating range in its public HBM3E product brief. Samsung says its HBM3E 12-layer technology improves thermal resistance by 11% over its predecessor and improves power efficiency by about 12%. These vendor statements establish that stack construction changes the thermal problem; they do not replace the accelerator vendor's lower system limit, sensor calibration, throttling policy or cooling qualification.

Run at least cold start, repeated warm reset, minimum/nominal/maximum board input, idle-to-bandwidth burst, sustained bandwidth, simultaneous compute-plus- memory activity, fault injection and recovery. Correlate memory errors and throttling with the voltage and temperature timeline. Archive the workload, firmware, memory speed, board revision, regulator configuration, cooling setup and probe locations with every result.

Release the package, PDN and cooling stack together #

An HBM3E sourcing request is normally an accelerator or system-package request, not a standalone memory-stock inquiry. The buyer may be told the memory vendor, capacity and stack height, but the accelerator supplier controls the qualified combination. A different HBM supplier, 8-high/12-high change or memory-speed bin can alter package qualification, power, thermals and firmware even when total capacity looks equivalent.

Do not approve “same output voltage,” “same 100 A module” or “same HBM3E capacity” as substitution evidence. A regulator alternate can change control response, telemetry, package escape and output-network requirements. An HBM package change can move the power and thermal envelope without exposing a standalone memory OPN to the OEM.

The HBM versus DDR sourcing guide explains why HBM is sourced through the accelerator rather than like a DIMM. The HBM manufacturing-gates article covers supply concentration. Neither replaces the package-specific power and validation record defined here.

Conclusion #

The correct HBM3E power design begins with the accelerator package document, not a generic voltage or a regulator shortlist. Freeze every HBM-related rail, derive current from the exact workload, allocate DC and AC tolerance, simulate the complete PDN, sense at the specified load plane, and validate fast voltage events alongside slow stack heating.

Procurement should release the accelerator, configured regulators, passives, board stack-up, monitoring firmware and cooling assembly as one qualified system. That boundary lets an engineer evaluate real alternates and lets a buyer request the evidence needed for an RFQ without inventing an unpublished accelerator BOM.

Official references #

• Micron HBM3E product page and current product positioning
• Micron HBM3E product brief: 24 GB/36 GB, 8-high/12-high specifications
• Samsung HBM3E product page: capacity, speed, thermal resistance and efficiency
• SK hynix 36 GB 12-layer HBM3E volume-production announcement
• AMD Versal Adaptive SoC PCB Design User Guide UG863, revision 1.12
• AMD Versal HBM Series recommended operating conditions DS960
• AMD target-impedance method and board-level PDN simulation guidance
• AMD current power-efficiency and reference-design evidence table
• MPS Versal HBM full power-management reference design, optimized for size
• MPS MPM3695-100 active product page and MPM3695GBH-100-0001 ordering code