GPU Load-Step Design: PDN, Bulk Caps and Remote Sense

Budget the event before selecting the regulator #

A GPU or AI-accelerator core rail can change current faster than the local multiphase regulator can replace the missing energy. The first nanoseconds are therefore a package-and-board PDN problem; the next interval belongs to local ceramics and bulk capacitors; only later does the controller increase phase current. Remote sense corrects the voltage seen at a defined load point, but it cannot cancel the instantaneous L·di/dt drop in the path.

That division of responsibility is the central design decision. Accelerator power engineers and BOM owners should freeze a load-step envelope, allocate the allowed voltage error by time and mechanism, then qualify the regulator, output network, copper path, sensing topology and test method as one assembly. This article does not infer an unpublished NVIDIA, AMD or other accelerator board BOM. The load profile and voltage limits must come from the processor owner's controlled specification or a measured, revision-specific workload.

The broader accelerator-board power-tree guide defines the 48/54 V, 12 V, core and HBM boundaries. Here the scope narrows to one high-current point-of-load rail and the evidence needed to release it.

Convert the rail tolerance into three engineering budgets #

Do not give the entire voltage tolerance to the transient. Split the processor limit into DC set-point and load-line error, switching ripple and noise, and dynamic undershoot/overshoot. If the rail specification allows a dynamic error of ΔV for a current step ΔI, a useful first target is:

Z_target = ΔV_dynamic ÷ ΔI_step

The result is not a complete PDN model, but it exposes impossible assumptions. A 20 mV dynamic budget and a 100 A step imply 0.2 mΩ over the frequency band assigned to the board. DC plane resistance, mounting inductance, capacitor ESR and the regulator's closed-loop output impedance all consume part of that number. A peak-current rating on a controller page does not prove it.

Use a second first-order check for the interval before inductor current catches up:

C_effective ≥ ΔI × Δt ÷ ΔV_capacitive

This is charge balance, not a capacitor order quantity. Δt must come from the measured or simulated control response, and the capacitance must be the effective value after DC bias, temperature, tolerance and ageing. Finally, estimate the edge loss separately:

ΔV_edge ≈ ΔI × ESR + L_path × di/dt

Adding far-away capacitance cannot repair an inductive edge. The solution may instead be shorter current loops, more vias, lower-inductance packages, closer MLCCs or a revised package/board partition.

Make each capacitor tier earn a defined time window #

The output network is not one lumped capacitance. On-package capacitance owns the fastest edge. Small, tightly mounted board MLCCs cover the next band. Larger ceramics and polymer or tantalum-polymer bulk parts supply charge while phase current ramps. The regulator then restores steady state. Input MLCCs and 12 V bulk capacitors have a different job: they keep the smart stages' input within range while the output power changes.

Place and simulate the tiers as physical networks. The same nominal capacitor at the regulator and at the package does not have the same impedance because the plane, vias and mounting loop sit in series with it. Likewise, replacing a polymer part with a lower-ESR alternative can reduce damping and raise an anti-resonance peak. “More microfarads” is not an approved substitution rule.

TI's PMP21887 is useful public evidence for method and scale, not a GPU prescription. The official 12-phase ASIC-core reference uses TPS536C7 with twelve CSD95480 stages and includes an onboard dynamic load. Its test report records a 100 A step on top of a 300 A static load, about 67 ns rise time, approximately 31 mV undershoot and settling to within 10 mV of the initial value in 2 µs under the documented build. Those numbers belong to that board, its 0.85 V output, 150 nH inductors, output network and test fixture.

MPS publishes a separate Agilex demonstration using MPM3698/MPM3699 modules. Its stated VCC/VCCP test condition is a 32.5 A step at 325 A/µs with 12 V input, 0.8 V output and 500 kHz switching. The documented capacitor set—32 × 47 µF MLCCs plus 4 × 330 µF polymer capacitors—is valuable because it keeps the transient result attached to a real capacitor population. It is not a reusable accelerator capacitor count.

For every proposed output network, return these four plots: effective capacitance versus bias and temperature, impedance versus frequency including mounting models, time-domain load-step response, and capacitor ripple-current/ temperature margin. Then name the approved series, case, dielectric, voltage rating, tolerance and ESR window in the BOM.

Remote sense closes DC error, not the entire PDN #

Differential remote sense tells the controller to regulate between two Kelvin points near the load. It can compensate for predictable DC drop through copper and connectors within the controller's sense range. It does not make the force path resistance disappear, and it does not deliver energy across its inductance during the load edge.

Choose the pickup point from the processor or package guidance. Where a vendor provides dedicated sense pins, use that documented pair and the required local network. Otherwise, define a repeatable load-plane location beside the approved decoupling field. Route sense positive and sense negative together, away from switch nodes, gate-drive traces and phase-current paths. Shielding with quiet planes can reduce coupled noise. Do not share the Kelvin connection with a high-current via or route it through removable connectors without an approved open-sense strategy.

TI's remote-sense layout guidance explicitly recommends taking feedback near the processor supply point, routing a differential pair in parallel, and keeping it away from switching lines. That guidance is consistent with current high-current controllers: active TPS536C7 lists remote sense, while active Renesas RAA228228 specifies differential remote sensing and ±0.5% closed-loop system accuracy over load, line and temperature. Neither statement proves the destination board. Sense input range, filtering, load-line implementation and failure behavior remain controller- and configuration-specific.

Validate local sense as a deliberate diagnostic option, not an automatic fallback. If the rail regulates locally but fails remotely, investigate pickup polarity, common-mode range, ground offset, sense filtering, damaged/open routes, firmware coefficients and noise coupling before changing compensation.

Select control response and capacitance together #

Controller response changes the energy the capacitors must provide. TI's TPS536C7 data sheet describes load insertion by pulling PWM pulses in more frequently and load release by delaying pulses until inductor current falls. Renesas RAA228228 documents dual-edge modulation and optional diode braking for faster transient response. MPS MPM3698 uses digital multiphase nonlinear control and active phase balancing. These are different control implementations, not interchangeable marketing labels.

Current, complete procurement examples illustrate the release boundary:

The TI reference still names CSD95480RWJ, but TI's February 2026 package addendum marks CSD95480RWJ and CSD95480RWJT NRND. A new design should not silently copy that stage. Ask TI for the current supported stage and require a new loss, current-sense, compensation, layout and transient report. This is a good example of why a still-useful reference design is not a current AVL.

Prove the load step with a controlled measurement contract #

An electronic load connected through long cables is usually measuring the cables. Put the dynamic load on the board or use a fixture with characterized inductance and a current monitor whose bandwidth supports the specified edge. Probe the rail with a low-inductance tip at the exact sense/load point. Record the 12 V input at the power stages, the core voltage, total load current, representative phase current and controller telemetry on a common time base.

Run both insertion and release. A design can pass undershoot yet fail overshoot because the inductor bank cannot shed stored energy quickly enough. Sweep the initial load, step amplitude, slew rate, repetition rate, input voltage, temperature and cooling condition. Include phase-add/drop boundaries and the highest permitted dynamic-voltage transition. Capture settling and ringing, not just the first peak.

The release record should answer:

1. Which workload or controlled load fixture produced ΔI and di/dt? 2. Where were voltage and current measured, with what probe bandwidth and de-embedding? 3. How much of the voltage window was consumed by DC/load line, ripple and the transient? 4. Which board revision, stack-up, controller image, stage, inductor and capacitor OPNs were installed? 5. Did every phase remain below electrical and thermal limits during repeated steps, not only one capture? 6. Do PMBus/AVSBus logs agree with the high-bandwidth measurement at the correct time scale, and are fault records retained?

Turn the validated PDN into an RFQ boundary #

Procurement should request an assembly-level evidence pack, not separate “equivalent” controller, capacitor and power-stage quotes. Freeze the exact controller OPN and programmed image; stage and inductor codes; every critical MLCC and bulk-capacitor series; approved alternates; board stack-up and copper weight; remote-sense routing/pickup definition; cooling condition; and the load-step test script with pass/fail plots.

Classify alternates by electrical consequence. A carrier-suffix change may be commercial only if the die and configuration are identical. A capacitor voltage rating, case, dielectric or ESR change alters the PDN. A different smart stage changes loss, current reporting and possibly loop behavior. A controller or NVM-image change reopens the entire qualification.

The multiphase-controller and smart-stage guide sets that controller-stage approval boundary. The existing decoupling-capacitor guide provides the frequency-domain and effective-capacitance sourcing method.

Conclusion #

A GPU load step is an energy-transfer problem with several owners. Budget the allowed rail error, assign the edge to package and local MLCCs, assign the handover interval to effective bulk capacitance, and let the regulator recover only on the time scale its measured control response supports. Use remote sense to regulate the defined load plane while keeping its Kelvin pair out of the switching field.

Release the rail only when the exact board, configuration, output network, sense topology and load fixture pass insertion and release across voltage, temperature and cooling corners. That evidence lets engineering choose an architecture and gives purchasing an RFQ that cannot be weakened by a superficially similar stage or capacitor substitution.

Official references #

• TI PMP21887 360 A static / 600 A peak ASIC-core reference design
• TI PMP21887 test report with documented 100 A dynamic-load response
• TI TPS536C7 active product page, data sheet and ordering information
• TI Multiphase Buck Design from Start to Finish, Part 1
• TI remote-sense placement and differential-routing guidance
• Renesas RAA228228 active 20-phase AVSBus/PMBus controller page
• MPS MPM3698 active product page and complete active part-number list
• MPS Agilex power-solution article with documented load-step and capacitor conditions