GPU and AI Accelerator Board Power: 48V, 12V, Core and HBM

Start with rail ownership, not an assumed accelerator BOM #

An AI accelerator board is not a single “GPU power rail.” It is a chain of energy domains: a protected 48 V or 54 V entry, an intermediate 12 V domain, high-current sub-volt regulation for compute, and separate rails for HBM, memory I/O, clocks, auxiliary logic and cooling. The processor vendor's published board implementation, if any, is the only authority for that exact platform. This guide therefore does not infer an NVIDIA, AMD or other accelerator BOM. It provides a board-level decision method for engineers and BOM owners selecting and validating the power path around an accelerator.

The decision before layout is to assign ownership to each conversion boundary: which assembly protects the high-voltage input, which module creates the 12 V plane, which multiphase rails serve the compute die, and which rails must remain independent for HBM and management. TI's February 2026 54 V eFuse reference design illustrates this hierarchy explicitly: a 40 V to 60 V protected input, then an intermediate-bus converter and local multiphase and point-of-load regulators for processor, GPU, FPGA, memory and BMC loads.

The earlier 54 V hot-swap and backplane protection guide ends at the protected board input. This article starts there and follows the board-level conversion and verification responsibilities downstream.

Keep 48/54 V protection separate from 12 V conversion #

At the card or board entry, define operating voltage, connector limits, inrush-energy budget, output capacitance, short-circuit response, enable order and telemetry owner. Those are protection decisions, not core-rail decisions. TI's PMP23496 8 kW hot-swap reference design uses an LM5066I controller for a nominal 54 V AI-server backplane path and documents a 40 V to 60 V input range, 150 A maximum output and 8.1 kW design point. Its current and capacitance values are reference-design conditions—not ratings to copy onto a different connector, MOSFET bank or thermal stack.

The next boundary is an intermediate-bus converter (IBC) or an equivalent board-level 48/54 V-to-12 V stage. Do not hide it inside a “VRM” line item: its fault isolation, conversion loss and available transient energy determine what the downstream multiphase rails can actually use. A design may distribute 12 V from a tray, create it locally from 48/54 V, or use another documented architecture; the selection must be tied to the platform power shelf and mechanical/thermal constraints.

Treat core and HBM as different validation problems #

The compute-core rail normally concentrates the highest local current and the tightest load-step requirement. It needs distributed phases, current sharing, remote or differential sensing where the load specification requires it, and measurement at the defined load plane—not merely at the regulator output. The controller, stage, inductor, input decoupling, output capacitors, routing and heatsink form one control-and-thermal system. Changing only the smart power stage is not an approved substitute because current reporting, switching loss, pinout, fault behavior and loop compensation may all change.

HBM-related supplies are not “spare phases” left over from the core VR. Their nominal voltage, sequence, ripple/noise budget and control ownership are platform-specific. Keep HBM enable/fault dependencies explicitly documented; never publish a generic HBM voltage or use a controller's general capability as proof of compatibility with a named accelerator.

TI's active TPS53688 is a concrete controller example rather than a recommended accelerator BOM: it supports two channels totaling up to eight phases, 4.5 V to 17 V input, 0.25 V to 5.5 V output, PMBus, remote sense and dynamic-voltage features. Its compatible interface and package must still be checked against the selected power stages and the platform's voltage-identification method. For a 12 V power-stage example, Infineon's active-preferred TDA22590XUMA1 is a 90 A OptiMOS integrated stage in a 4 mm × 6 mm PG-UFLGA-34 package; the vendor lists 4.25 V to 16 V input, current reporting, fault identification and an output range down to 0.225 V. It is not a drop-in replacement for a stage specified on another board.

Validate a disturbance across the whole power tree #

Run each important event as a chain, with synchronized probes and an agreed pass/fail table. A core load step can expose 12 V droop, an IBC current limit, input-path foldback, output-capacitor ESR/ESL, phase-current imbalance or a remote-sense placement error. Looking only at one oscilloscope channel can make an upstream failure look like a controller problem.

1. Establish the 48/54 V input at its approved minimum, nominal and maximum conditions, including the applicable source impedance. 2. Capture the 12 V plane at the IBC output and at the local VR input during the defined core-load transient. 3. Measure the core rail at the specified remote-sense/load plane; separately record phase current, switch-node behavior and component temperatures. 4. Exercise enable, reset, brownout and fault recovery with HBM and auxiliary rails observed as independent sequence participants. 5. Archive scope setup, firmware/NVM image, board revision, cooling condition and exact assembly OPNs with the result.

This makes substitutions auditable. TI notes that TPS53688 programmable parameters are configured through PMBus and its toolchain supports configuration and monitoring. A replacement controller, a changed stage or a different NVM image therefore requires a controlled validation event, not only a purchase approval.

Build the RFQ around assemblies and approval boundaries #

For procurement, group the request into protected-entry, IBC, core VR, HBM/ auxiliary and monitoring assemblies. For every line, request the full ordering code, manufacturer, package, reel/tray condition, date-code constraint, quantity, lot traceability and required ship date. Ask engineering to mark three categories: exact-only, pre-approved alternate, and design review required. A “same voltage/current” stage belongs in the third category until pinout, PWM/telemetry behavior, current sense, thermal path, passives and firmware have been checked.

The TDA22590 sourcing guide is useful when an approved bill already calls for that family. The AI server power semiconductor market guide addresses broader supply risk; neither replaces a board revision-specific VR qualification record.

Conclusion #

A credible accelerator-board power plan draws hard boundaries: protect 48/54 V, convert and observe the 12 V domain, regulate compute locally, and treat HBM and auxiliary rails as independently sequenced loads. Select controllers and power stages only against the platform's documented interface, control and thermal requirements. Then validate a load disturbance across the complete tree and RFQ the approved assembly—not a collection of superficially similar components.

Official references #

• TI TIDA-050090: 54 V 5 kW Power Path Protection Reference Design for AI Data Centers
• TI PMP23496: 8 kW Hot-Swap Reference Design for 48 V AI Servers
• TI TPS53688 active product page and datasheet
• Infineon TDA22590 product page and orderable code details