Digital Power Control, Current Sensing and Metering

Assign each measurement a job before choosing an IC #

An AI rack needs several kinds of electrical truth, and they are not interchangeable. A converter control loop needs a low-latency current and voltage signal. Autonomous protection needs a bounded trip path even when firmware is stalled. The rack controller needs telemetry for health and fault correlation. Operators may also need accumulated energy and input power-quality records. One measurement chain rarely satisfies all four jobs.

This guide is for rack-power, converter-control and instrumentation engineers, plus BOM owners who must freeze the measurable requirements in an RFQ. The practical conclusion is to choose by decision latency, electrical domain and evidence quality, not by ADC resolution alone. Keep fast control local to the power stage, place a high-common-mode monitor on each important 48/54V branch, aggregate selected low-voltage rails near the load, and use a dedicated polyphase metering front end at the AC boundary when power quality or auditable energy matters.

The diagram is a selection map, not a claim about an unpublished accelerator board BOM. Exact rail count, sensing location, isolation boundary and reporting rate belong in the platform specification.

Four device classes solve different problems #

The following parts are current, documented examples of the four roles. They are not drop-in alternatives.

For a compact single-loop converter, Infineon's active XDPP1100Q024XUMA1 is another useful controller reference. The 24-pin VQFN device provides six high-resolution DPWM outputs, one high-speed feedback rail, dedicated voltage and current-sense ADC resources and PMBus 1.3. Its 78.125 ps DPWM resolution is a timing resource; it does not state end-to-end output accuracy without the sense network, calibration and power-stage model.

The controller boundary deserves special attention. TI's UCD3138A has dedicated digital power peripherals for the control loops and a separate general-purpose ADC for monitoring. Treating the latter as if it were the feedback path loses the architectural reason the part exists. The same distinction should appear in requirements: control-loop bandwidth and stability belong to the converter release, while telemetry update rate and register accuracy belong to the management release. For bus command and fault-record design, see the related PMBus and AVSBus telemetry guide.

Build the current-sense error budget from the copper outward #

For a resistive shunt, the two first-order equations are simple:

Vshunt = I × Rshunt and Ploss = I² × Rshunt.

The trade-off is not. A larger shunt voltage improves signal-to-offset ratio but raises conduction loss and temperature. A smaller resistor reduces heat but makes amplifier offset, thermoelectric effects and layout resistance more important. At hundreds of amperes, the shunt may be a busbar element or a calibrated conductor rather than a catalogue chip resistor.

Start the released error budget at the required trip or reporting point. Include shunt initial tolerance, temperature coefficient, self-heating, sense-amplifier offset and gain error, ADC/reference error, common-mode effects, PCB parasitics and calibration residual. Add worst-case terms for a safety or protection threshold unless independence is justified; root-sum-square treatment is not a default permission to hide correlated drift.

Use four-wire Kelvin connections at the shunt. Route the two sense traces as a quiet pair from the defined measurement points, not from arbitrary power copper. Then test common-mode steps and PWM edge coupling at the maximum qualified bus slew rate. A monitor may meet DC accuracy while producing a transient alert or sample error because the layout exposes it to switching fields.

The INA228 illustrates why complete limits matter more than the headline bit count. Its data sheet specifies two shunt ranges, ±163.84 mV and ±40.96 mV, conversion times from 50 µs to 4.12 ms, averaging from 1 to 1024 and an 85V common-mode ceiling. Shorter conversion gives faster visibility; longer conversion and averaging reduce noise. Freeze the chosen range, conversion time and averaging in firmware requirements because all three change the effective measurement and alert behavior.

Separate protection, telemetry and accounting #

A robust design gives each measured quantity an explicit consumer:

Energy is an integration problem: E = Σ(Vk × Ik × Δt). Voltage and current error are only part of the result. Sampling alignment, timebase accuracy, accumulator width, reset behavior, rollover handling, missed communications and sign convention all affect the reported energy. Ask whether the device accumulates internally or the host integrates samples; the latter makes bus latency and lost transactions part of the metrology chain.

Microchip's PAC1934 is useful for attributing energy among several 12V or lower board rails. Its four channels and long integration window reduce host traffic, but the 32V input ceiling makes it the wrong device for direct 54V measurement. TI's INA228 covers that higher-voltage branch with margin up to 85V, but it is a single-channel device. The architecture therefore changes with rail count and voltage domain; a four-channel part is not automatically a smaller BOM if it requires extra dividers, protection or isolation.

At the facility interface, ADE9430 measures a different class of evidence. It supports polyphase active, reactive and apparent power/energy, RMS, power factor and power-quality functions, and accepts current transformers or Rogowski coils with the required external network. Analog Devices states that Class 0.2 metering is achievable with standard external components. That is a system design starting point, not a certification claim: transformer ratio and phase error, voltage divider, PCB isolation, calibration, software library and the target standard still require qualification. Pair this boundary with the 30kW three-phase PFC architecture when defining the shelf input measurement point.

Make calibration and fault records traceable #

Calibration must be a controlled manufacturing operation, not an unexplained offset in firmware. Record the reference instrument, source conditions, temperature, fixture resistance, calibration coefficients, serial or lot association and pass limits. Protect coefficients against accidental overwrite and make the service interface report their version.

For fault reconstruction, preserve both the fast event and the slower context. A controller can latch the first hardware fault while a branch monitor records pre-event current and voltage and the rack controller adds shelf, fan and temperature state. Define one timebase or a correlation method. Otherwise a high-resolution current value beside an untrustworthy timestamp does not explain which event came first.

Do not place primary protection behind PMBus, SMBus or a host daemon. A digital alert is valuable for secondary response and evidence, but software latency, bus arbitration and a failed controller must not prevent the locally required safe action. The interconnect and converter choices are covered separately in the 48/54V-to-12V intermediate-bus guide.

Freeze complete orderable codes and RFQ evidence #

Do not release a family name as a BOM line. Current official pages support the following procurement positions as of 8 September 2026:

The RFQ should also state bus maximum and transient voltage, current range and crest factor, shunt or sensor construction, isolation boundary, channel count, required accuracy over temperature, bandwidth or conversion time, alert latency, interface voltage, register-map/firmware revision, calibration method, traceability, package, temperature grade and packing quantity. For approved alternates, require a comparison of common-mode range, alert semantics, accumulator width, address options, conversion timing and pinout. Similar resolution is not an alternate qualification.

Conclusion #

Digital power observability is reliable only when control, protection, telemetry and accounting remain distinct. Put the fastest sense path inside the converter control and protection boundary; use an 85V monitor for important 48/54V branches; use multi-channel monitors where lower-voltage rail attribution matters; and use a metrology front end where AC energy and power quality must be defensible. Release the system with an error budget, calibration record, timestamp strategy and complete orderable codes—not a list of ADC bit counts.

Official references #

• TI UCD3138A digital power controller product page
• TI UCD3138A data sheet
• Infineon XDPP1100-Q024 product page
• Infineon XDPP1100 data sheet
• TI INA228 85V current and power monitor product page
• TI INA228 data sheet and orderable information
• Microchip PAC1934 four-channel power monitor product page
• Microchip PAC1931 family data sheet
• Analog Devices ADE9430 polyphase metering IC product page
• Analog Devices ADE9430 data sheet