800VDC-to-54V/12V Isolated DC/DC Design

Freeze the output contract before choosing the topology #

An isolated converter between an 800V rack bus and an accelerator tray is not just a high-ratio transformer. It owns a safety boundary, converts a single or split high-voltage feed, survives bus insertion and faults, and presents a low-voltage rail whose tolerance and transient behavior determine every stage downstream. The first decision is therefore 50/54V versus 12V, not GaN versus silicon or LLC versus another resonant topology.

This guide is for rack-power architects, DC/DC and magnetics engineers, and BOM owners preparing a qualification build. A 50/54V output preserves a familiar medium-voltage tray ecosystem and keeps current manageable, at the cost of an additional conversion stage near the accelerator. A 12V output removes that stage but moves much more current through the board. At an ideal 6kW, the rail current is 7.5A at 800V, about 111A at 54V, and 500A at 12V. Copper, connectors, rectification and fault energy—not just converter efficiency—decide which path works.

The public hardware evidence must also be named accurately. Infineon's March 2026 high-voltage IBC announcement documents 800V/±400V to 50V and 800V to 12V reference designs; it does not document a 54V version. A 54V procurement specification must therefore define its own nominal voltage, steady-state range, startup overshoot and downstream acceptance window rather than relabel the 50V demonstration. Vendor Reference Design

Why series-stacked building blocks are practical—and demanding #

Current public designs avoid placing the full 800V across one 650V switching bridge. Infineon's 6kW 800V-to-50V demonstration uses two 3kW, 400V-to-50V building blocks in input-series, output-parallel (ISOP). The OCP-hosted Renesas white paper describes the same scalable pattern for a 12kW, 800V-to-48V system: each 6kW unit stacks two 3kW, 400V-to-48V LLC DCX blocks, then two 6kW units are paralleled.

ISOP divides switch voltage stress and combines output current, but it creates two control obligations that a schematic block diagram can hide:

• Input-voltage sharing: each series block must remain near its intended

share during startup, steady state, a load step and a fault. Magnetizing tolerance, dead-time mismatch, bias timing and unequal output impedance can move the midpoint.

• Output-current sharing: paralleled rectifier paths, magnetics and copper

must share current without one module reaching its thermal or current limit first. Tight turns ratio alone is not proof of system sharing.

TI's PMP41037 is useful independent evidence at a smaller power level. It is a 1kW isolated, bidirectional 800V-to-12V DCX with a 760–840V input range, 12V/84A output, serial half bridge and active voltage-balancing control. TI reports efficiency above 98%; that measured boundary belongs to PMP41037, not to a scaled 6kW production design. Vendor Reference Design

Treat 50V and 54V as different contracts #

The attraction of the higher output rail is reuse: backplane protection, downstream 48/54V IBCs and board-level converters already exist. But “48V class” does not make 48V, 50V and 54V interchangeable. A downstream converter may be rated to 60V or 80V yet still have a narrower operating, hot-swap or transient window. The RFQ needs four numbers: nominal output, continuous range, startup/turn-off excursion, and permitted transient duration.

An unregulated LLC DCX can be compelling when the upstream 800V bus is bounded and the downstream stage owns tight regulation. The OCP/Renesas paper explains that an LLC DCX runs at or near resonance with a turns-ratio-defined conversion, using primary-side ZVS and secondary-side ZCS in its described implementation. That simplifies the fast regulation loop, but it transfers responsibility to the interface specification. Line variation, component tolerance and load dependence must all fit the receiving converter's input window.

Choose a regulated high-voltage IBC when the bus range or downstream window is too wide for that contract, when controlled ramp is valuable, or when the platform needs a defined current-limit behavior at the tray boundary. Do not assume “open loop” means “uncontrolled”: input balance, synchronous-rectifier timing, startup, telemetry and fault shutdown still require deliberate control.

The 12V route trades stages for current #

Direct 800V-to-12V conversion can remove the separate 50/54V-to-12V stage. Its benefit has to be measured at the system boundary, however. At 6kW, a 12V rail is already 500A before considering margin. A small improvement in conversion loss can be erased by connector resistance, output-bus copper, rectifier loss or a longer path to the point-of-load stages.

The 12V route is strongest when the HV IBC can sit very close to the load, current is divided across many short output paths, and the board and cooling mechanical design are developed with the converter. Infineon's 8mm-high 12V demo is specifically evidence for thin form factors; it is not evidence that an arbitrary motherboard can accept its current. For tray designs that retain a 50/54V boundary, the downstream choice is a separate problem; our 48/54V-to-12V intermediate-bus guide covers that lower-voltage stage and its transient ownership.

Isolation, magnetics and common-mode current are one design #

The transformer is both an energy-transfer element and the reinforced or basic isolation barrier selected by the end-equipment safety design. Creepage and clearance cannot be copied from a reference board as a single magic dimension: working voltage, overvoltage category, pollution degree, material group, altitude, insulation system and the applicable equipment standard all affect the requirement. The PCB stack, core, winding construction, slots, coating and connector must be reviewed as one barrier.

Matrix transformers divide secondary current among multiple winding/rectifier cells and can make leakage and thermal paths repeatable. The OCP/Renesas paper describes inter-phase flux cancellation, controlled leakage and PCB-integrated windings as its density mechanisms. Those benefits also make the PCB and magnetics vendor part of the electrical design: copper thickness, dielectric, registration, core gap and assembly pressure belong in the controlled build specification.

Fast GaN edges add a separate common-mode problem. Transformer interwinding capacitance, heat-sink capacitance and isolated-bias capacitance return dv/dt current across the barrier. Measure primary and secondary common-mode current, driver CMTI margin, drain overshoot and emissions with the intended cooling hardware installed. Slowing an edge can improve EMI but increase switching loss; shielding can reduce one coupling path while adding capacitance elsewhere. This is a layout-and-thermal optimization, not a gate-resistor-only exercise.

Startup and faults need explicit owners #

An 800V IBC should never depend on the supervisory processor to stop a destructive switching event. Fast overcurrent, gate-driver undervoltage and illegal bridge states need local hardware action. Slower functions—input midpoint supervision, thermal derating, retry policy, PMBus reporting and rack coordination—can sit in the digital controller or host layer. The sequence must also work with no output power available, so auxiliary-bias startup is a first page requirement, not a late BOM detail.

The OCP/Renesas implementation places the MCU on secondary ground, transfers primary PWM across galvanic isolation and uses isolated high-voltage gate drivers. It also calls out the auxiliary supply's role during connection and disconnection from the 800V bus. TI's 300W PMP41133 is not a main AI IBC, but its 450–800V (950V maximum stated range) to 48V auxiliary design is useful evidence for this housekeeping function: it includes high-voltage startup, UCC5350 isolated gate drive and an ISOM8110 opto-emulator feedback path.

Qualification should inject faults, not merely observe a successful ramp:

• start at minimum and maximum bus voltage, with pre-biased output and the

downstream converter both enabled and disabled;

• force a mismatch between series blocks and verify midpoint limits before

switch stress exceeds the design value;

• short one output branch, open one current-share path, and test loss of

isolated bias, current feedback and temperature sensing;

• repeat load release and overload at hot and cold corners to confirm that the

LLC remains in its intended soft-switching region;

• verify the rack disconnect clears sustained faults while local protection

handles the first switching cycles;

• measure stored-energy discharge and touch-safe timing after commanded and

fault shutdown.

Release orderable parts by function, not by headline voltage #

Reference-design identifiers are not production converter order codes. Build the BOM around qualified functions—primary switch, gate drive, controller, isolated sensing, synchronous rectification and auxiliary bias—and preserve the exact ordering suffix. The examples below are current, traceable parts as of September 4, 2026; inclusion means the cited official design or product page supports the stated role, not that the parts are interchangeable.

Do not put an unreleased semiconductor into an approved vendor list. The OCP/Renesas paper explicitly labels its RBE024N08R1SZN6 80V synchronous- rectifier MOSFET as “in development.” Keep it as reference-design context until Renesas publishes a current orderable product page and lifecycle state.

RFQ and validation release checklist #

A useful converter RFQ is a boundary specification plus an evidence request. Send the supplier the following as one controlled package:

1. Input contract: 0–800V or ±400V topology, continuous range, surge and ride-through waveform, source impedance, precharge and rack-disconnect behavior. 2. Output contract: exact 50V, 54V or 12V nominal; steady and transient limits; peak-power magnitude/duration; pre-bias; discharge time; ORing and current-share requirements. 3. Isolation contract: basic or reinforced function, working and transient voltage, altitude, pollution degree, insulation system, production hipot method and the governing end-equipment standard. 4. Thermal/mechanical contract: cold-plate or airflow boundary, coolant or inlet range, pressure/flatness, maximum height, connector and busbar temperature-rise limits, and hotspot telemetry. 5. Protection evidence: cycle-level OCP and driver response, midpoint imbalance limits, output short behavior, retry/latch policy, safe discharge and fault-log definitions. 6. Manufacturing evidence: full orderable BOM with lifecycle status, transformer construction drawing, controlled PCB stack, approved alternates, firmware/configuration revision, lot traceability and change-notification terms. 7. Test data: efficiency and temperature maps across input/load corners, load-step waveforms, imbalance tests, conducted/radiated EMI with production cooling hardware, isolation certificates and reliability plan.

The upstream boundary belongs to the three-phase rectifier and bus controller; see the 30kW three-phase PFC guide for that interface. For the vendor-specific roadmap and its three conversion routes, use the Infineon 800V HVDC architecture overview.

Conclusion #

The defensible choice is the output architecture whose complete interface can be released and tested. A 50/54V rail buys current margin and ecosystem reuse; a 12V rail buys one fewer conversion stage but demands a much more aggressive low-voltage PDN. In either case, series-block balance, isolation construction, auxiliary startup and layered fault response are first-order requirements. Use public reference designs as measured evidence, preserve their exact boundaries, and ask the supplier to close every gap between the demo and the production rack.

RFQs welcome. RFQ: sales@limchip.com

Official references #

• Open Compute Project. Powering the Next Era of AI: Google, Microsoft and NVIDIA Align on LVDC, August 11, 2026.
• Open Compute Project / Renesas. Power Architecture Evolution in Data Centers, September 25, 2025.
• Infineon. CoolGaN-based HV IBC Reference Designs for 800VDC AI Data Centers, March 17, 2026.
• Infineon. Intermediate Bus Converter Solutions for AI Data Centers.
• Infineon. XDPP1188-200C Digital Power Controller Product Page and XDPP1188-200C Datasheet.
• Infineon. IGT65R025D2 650V CoolGaN G5 Product Page.
• Texas Instruments. PMP41037 1kW Isolated 800V-to-12V Bidirectional DCX.
• Texas Instruments. TMS320F280039C Real-Time MCU Product Page and F280039CSPZR Orderable Detail.
• Texas Instruments. PMP41133 800V-to-48V Auxiliary DC/DC Reference Design.
• Texas Instruments. AMC1311 Reinforced-Isolated Voltage-Sense Amplifier.
• Renesas. TP65H030G4PRS 650V SuperGaN FET Product Page and HIP2211 Half-Bridge Driver Product Page.