54V AI Server Hot-Swap and Backplane Protection

Protect the connector, FET bank and load as one system #

A 54V AI accelerator tray can no longer treat hot-swap as a small housekeeping circuit. TI's current PMP23496 reference design carries 150A RMS at 54V—8.1kW—at a stated 70°C ambient, while its newer TIDA-050090 demonstrates a 54V, 5kW path with six stacked eFuses. Those are reference-design results under documented conditions, not universal ratings, but they establish the scale of the problem: the connector, busbar clip, sense element, pass devices, bulk capacitance and downstream converters form one protection system.

This article is for power architects and BOM owners deciding between a controller plus external MOSFET bank and stacked integrated eFuses. The practical output is a protection specification and an RFQ that names the controller, package, packing code, FET qualification and validation conditions—not merely “54V hot swap.”

Start with the energy and fault envelope #

Define four operating cases before selecting silicon:

1. Normal insertion. The controller must charge an initially empty output capacitor without collapsing the shared bus or violating the pass FETs' linear safe operating area (SOA). 2. Steady load and transients. GPU load steps must not be mistaken for faults. Current-limit delay, telemetry averaging and upstream droop all matter. 3. Overload or hot short. The gate must discharge quickly enough to interrupt a low-impedance fault, including the effective gate capacitance of many parallel MOSFETs. 4. Abnormal backplane events. Input overshoot, connector bounce, reverse current, brownout and repeated retry can each stress a different component.

Capacitance turns insertion into an energy problem. A 5mF output charged to 54V stores about 7.3J (`½CV²`). That number does not equal MOSFET dissipation—the source, ramp shape, load and parasitics change the split—but it shows why a single DC current rating is insufficient. ADI's EVAL-LTC4287-A1Z is populated as a 54V, 72A, 5mF design and provides footprints for up to eight parallel sense resistors and four MOSFETs per channel. Treat those values as a documented starting point, then recalculate for the production capacitance, minimum input, maximum input, temperature and airflow.

What belongs in the 54V protection path #

OCP's current Open Rack material documents a 48V busbar ecosystem, while the OCP-hosted MGX rack specification permits a 40V to 59.5V busbar and notes typical 48V, 51V or 54V power-shelf outputs. Do not turn “48V architecture” into a 48.0V component limit. The protection path must cover the specified steady range, droop compensation and credible transient envelope.

MOSFET SOA is the central sizing check #

During a controlled ramp, an external N-channel MOSFET can simultaneously carry high current and drop tens of volts. Its switching `RDS(on)` rating does not describe survival in that linear operating region. Use the manufacturer's SOA curves at the intended pulse duration, then derate for junction temperature, device variation and unequal sharing. A bank that shares well at low `RDS(on)` may not share equally during linear operation.

The controller must also be able to pull down the combined gate charge during a hot short. TI's PMP23496 explicitly validates turn-off of nine MOSFETs with an effective 150nF input capacitance. That result belongs to the published board and test conditions; changing FETs, gate resistors, layout or clamp network requires new validation.

Integrated eFuses change the partition. TI's TIDA-050090 uses one TPS1689 and five TPS1685 devices in parallel for a 54V, 5kW design and reports 100A RMS at 55°C ambient without external airflow. The integration reduces external gate-drive and protection components, but stacking still demands the documented current- sharing, startup and thermal layout. It is an architecture alternative, not an automatic replacement for an external-FET design.

Current controller choices and exact order codes #

The following devices are current candidates checked against manufacturer pages on August 8, 2026. They are not footprint or firmware substitutes.

The LM5066I path has direct public high-power server evidence. LTC4287 offers a documented 54V/72A/5mF evaluation configuration and dual-gate architecture. XDP710-002 provides programmable digital SOA control and detailed telemetry. Choose by the fault strategy, telemetry owner, FET bank and validation flow—not by input-voltage range alone.

Backplane and firmware details that cause field failures #

• Connector sequencing: ensure ground and detection contacts behave as the

controller assumes. Contact bounce during the ramp can restart or partially discharge the load.

• Kelvin sensing: route the sense inputs directly to the shunt terminals.

Infineon's XDP710 guidance also separates SOURCE sensing from the output power plane; milliohms of shared copper matter at 100A.

• Retry policy: repeated auto-retry can heat a failed FET bank more than one

latched event. Define retry count, delay and service behavior.

• PMBus ownership: lock addresses, scaling coefficients, warning thresholds,

fault-log retention and the production configuration checksum.

• Reverse energy: decide whether a charged tray may feed an unpowered bus.

Hot-swap control and ideal-diode/reverse-blocking functions are not synonymous.

• Power-good sequencing: do not enable multi-kilowatt downstream converters

until the protected output has reached its verified threshold.

Validation and RFQ checklist #

Test cold insertion at maximum input and capacitance, hot insertion with the expected connector, minimum-input startup, load transients, overload, output hot short, input surge, brownout, retry and commanded shutdown. Repeat across ambient, airflow and component tolerances. Measure FET case or junction-correlated temperature, shunt balance, gate waveforms, bus droop and fault telemetry.

The RFQ should include the full controller OPN, quantity, packing requirement, temperature range, approved FET and shunt part numbers, output capacitance, maximum steady current, surge profile and whether substitutes may change firmware or qualification. For a reference-design build, identify the reference revision and list every deliberate BOM deviation.

Conclusion #

A robust 54V AI-server input is an energy-management and fault-isolation design, not a large switch. Specify the bus and connector envelope, calculate stored energy, validate every MOSFET in linear SOA, coordinate short-circuit turn-off and record PMBus behavior. LM5066I, LTC4287 and XDP710-002 represent three current external-FET controller paths; stacked TPS1689/TPS1685 eFuses provide a newer integrated alternative. The right choice is the one whose complete power path survives insertion, load steps and faults under production thermal conditions.

For the longer-term rack-voltage transition, the companion Infineon 800V HVDC AI server architecture guide places this 48/54V protection stage in the wider grid-to-core power chain.

Official references #

• TI PMP23496 8kW hot-swap reference design for 48V AI servers
• TI TIDA-050090 54V 5kW power-path protection reference design
• TI LM5066I product page and active orderable models
• Analog Devices LTC4287 product page, lifecycle and order models
• Analog Devices EVAL-LTC4287 54V, 72A, 5mF evaluation platform
• Infineon XDP710-002 product page and full OPN
• Open Compute Project Open Rack specifications and designs
• OCP MGX accelerated computing rack and trays specification