| Data Rate | 1 to 20 kbps (1 to 20 kBd, LIN NRZ signaling) |
| Supply Current | Sleep IBAT: 3 uA typical, 15 uA maximum, LIN=WAKE_N=VBAT, TXD=SLP_N=0 V. Normal recessive: 380 uA typical, 600 uA maximum. Typical VBAT=12 V, ambient 25 C |
| ESD Protection | LIN, WAKE_N, VBAT and INH: HBM +/-8 kV, IEC61000-4-2 +/-4 kV |
| Operating Temperature | -40 to +125 C ambient; -40 to +150 C junction |
| Protocol | LIN 2.0 / 2.1 / 2.2 / 2.2A; ISO 17987-4:2016 (12 V); SAE J2602 |
| Transmitter / Receiver Channels | 1 LIN transmitter / 1 LIN receiver; single-wire physical layer |
| Supply Voltage (VBAT) | 5.5 to 27 V operating range |
| Logic Interface | TXD and SLP_N high input >=2.0 V, low input <=0.8 V; RXD open-drain output; external pull-up required; no separate VIO supply pin |
| Bus Fault Voltage | LIN pin absolute maximum -42 to +42 V |
| Operating Modes | Normal, standby, sleep and power-on states; controlled by SLP_N |
| Wake-Up | Remote LIN dominant wake-up 30 to 150 us, 65 us typical; local WAKE_N dominant wake-up 7 to 50 us, 22 us typical |
| Receiver Threshold | Dominant <=0.4 x VBAT; recessive >=0.6 x VBAT |
| Propagation Delay | Receiver delay 6 us maximum; symmetry -2 to +2 us; RXD load 20 pF with 2.4 kohm pull-up |
| Protection | TXD dominant timeout 27 to 90 ms, 52 ms typical; LIN current limit; thermal shutdown; battery undervoltage |
| Bus Termination | Internal slave pull-up resistance 20 to 60 kohm, 30 kohm typical at VBAT=12 V; master needs external resistor and series diode |
| Power Management | INH high-voltage output controls an external regulator; INH is high impedance in sleep |
| Qualification | AEC-Q100 qualified, per manufacturer datasheet |
| Package Details | 8-pin SOP; body 4.9 x 3.9 mm typical; lead span 6.0 mm typical; pitch 1.27 mm; height 1.8 mm maximum |
