NOR Flash retains data without power and is often used for boot code, firmware and information that is read frequently but changed infrequently. Its strength is access to a small amount of data at a chosen address; with a suitable host, code can also run directly from external NOR through execute in place (XIP). The design tradeoff lies in how that data is changed. Reading, programming and erasing are three different operations, with different granularity and timing. Understanding those operations explains where NOR belongs in a system more clearly than capacity and SPI lane count alone.
Article contents
- Array connections explain the random-read advantage
- A random read is different from programming and erasing
- XIP is a host capability as well as a Flash capability
- From wafer cells to a packaged NOR device
- Planar NOR and 3D NOR are at different stages
- Supplier names matter less than the job the memory performs
- Turn the architecture into an exact device choice
- Key references
Array connections explain the random-read advantage #
A flash cell stores charge that changes a transistor's threshold voltage. Sense circuitry reads the resulting electrical state to distinguish stored values. Manufacturers use different cell designs, including floating-gate and split-gate approaches, so one transistor cross section cannot stand for every NOR product. The array connection is the more useful comparison for a system designer: a NOR array provides a relatively independent path from a selected cell to a bit line, whereas a NAND array places multiple cells in a series string.
That connection helps NOR retrieve a small amount of data from a chosen address. NAND's series structure supports dense storage, but a host usually reads it in pages and manages data through a controller or buffer. The drawing describes access topology, not an assertion that every NOR cell can be rewritten individually like RAM. Nor does the NAND structure prevent a processor from booting from NAND: a compatible boot ROM and controller can load a boot image from it. The practical question is how the host obtains code, how much data must be stored, and which management work sits in hardware or software.
| NOR Flash | NAND Flash |
|---|---|
| Random reads: well suited to them; a compatible controller may map NOR for XIP | Random reads: usually obtains a page first and then uses a buffer or RAM |
| Large data: cost per bit generally becomes less attractive as capacity rises | Large data: dense storage is generally the stronger role |
| Host work: boot commands, mapped-read mode, write protection and firmware updates | Host work: raw NAND also needs error correction, bad-block handling and mapping; managed devices such as eMMC and UFS perform some of that work internally |
These are typical roles, not guaranteed speed, endurance or price figures for an individual part. Parallel and serial NOR use different external interfaces. Even when the underlying array supports efficient random access, the host bus and controller still set the latency and bandwidth the application actually sees.
A random read is different from programming and erasing #
The host can start a read at a specified address, but it cannot normally overwrite stored content as it would in RAM. In common serial NOR designs, erasure returns bits in a selected region to logical 1. Page programming changes selected 1 bits to 0. Restoring a programmed 0 to 1 requires an erase of the region containing it. Reads, page programs, and sector or block erases therefore touch different amounts of data and have different completion times.
There is no universal NOR page or erase size. Infineon's information for S25FL256LAGBHV020, for example, specifies a 256-byte page-program buffer and uniform 4 KB sectors. Another family may offer different programming limits, erase choices or status-register behavior. An update-time calculation must account for write enable, erase operations, programming and status polling, plus any use of erase suspend. A maximum sequential read rate is not a firmware update rate.
These constraints shape the memory map. A product that updates code in the field should separate boot code, application images, configuration and rollback metadata with erase boundaries in mind. Metadata that must change independently should not be trapped in the same erase region as indispensable boot instructions. The firmware also needs a defined response to power loss during an update. Reserving two images can help a recovery design, but only when the actual image sizes, flash layout and host boot sequence permit it. A faster SPI clock cannot compensate for a memory map that makes a safe update impossible.
Endurance is similarly workload dependent. Rewriting one sector repeatedly is different from occasionally updating a complete firmware image. Retention can also depend on temperature and the amount of prior cycling. Read an endurance or retention figure together with its stated conditions and the exact device family; a figure published for one NOR product is not a capability shared by every NOR part. If an application writes frequently, model how often each erase region will be cycled rather than relying on an aggregate amount of data written.
XIP is a host capability as well as a Flash capability #
Execute in place means the processor fetches instructions from nonvolatile memory mapped into its address space. Parallel NOR may expose an addressable path through an external memory bus. For serial NOR, a QSPI, OSPI or comparable controller has to translate a memory-mapped access into the Flash read command, address phase and data transfer. The processor's boot ROM, the controller configuration and the Flash device's supported read modes must work together. Soldering an SPI NOR device onto a board does not, by itself, make XIP available.
ST's AN5188 application note describes execution from mapped external QSPI or OSPI Flash separately from copying code to RAM and executing it there. XIP may reduce the amount of RAM required for the whole code image, but serial transfer latency, cache behavior and interrupt response still need measurement on the target board. Copying code first occupies more RAM; the copied instructions then follow the RAM access path. Even in an XIP design, the stack, writable data and some time-critical routines may still reside in RAM.
The number of interface lanes is only one part of execution performance. Dummy cycles in a read command, clock frequency, controller mode support, supply voltage and PCB signal integrity can all limit the useful rate. A host may support a four-lane read mode in an application but only a more restricted command during its earliest boot stage. Before selecting a wider-interface device, inspect the processor's boot documentation and controller modes, then match them against the complete Flash ordering code and the commands it supports. Confirm cold boot and code execution on the target hardware rather than inferring either from an interface label.
From wafer cells to a packaged NOR device #
Manufacturing NOR involves more than arranging storage transistors in a grid. The array needs word and bit lines, address decoding, sense amplifiers, circuits that supply the voltages required for programming and erasure, and an external interface. Two chips of equal capacity may make different choices in cell design, peripheral circuitry and optional features. A cross section published by one manufacturer explains that process; it cannot be treated as a cross section of every other NOR family.
Those circuits help explain why datasheets give separate read, page-program and erase timings. Reading senses a stored state, whereas programming and erasure must change that state and preserve it over time. The operations differ in speed and electrical stress. Wafer probing, testing after packaging and validation over the specified operating temperature range all serve the required read margin, cycling endurance and retention. Successful boot at room temperature does not establish that a device will meet an automotive or industrial product's temperature and update requirements.
Smaller process dimensions or more capacity on one die do not improve every characteristic automatically. A denser array must still be assessed alongside reliability, cost, interface bandwidth and available packages. The engineering choice is an exact, qualified device, not an abstract process node.
Planar NOR and 3D NOR are at different stages #
Planar NOR has continued to evolve through cell, process and circuit changes. Higher density has to be balanced with decoding, read performance and reliability. NAND's widespread move to vertical stacks does not establish that all NOR products will follow the same manufacturing route. Nor can a single process-node number tell a designer that NOR has reached one universal physical limit. For a current board, interface behavior, capacity, timing and temperature grade are closer to the actual choice than a headline about nanometres.
3D NOR has moved beyond a research concept, but a public launch and routine availability of a particular ordering code are different milestones. Macronix said in its 2024 annual report that it launched a 3D NOR product at electronica that year, while continuing to develop higher-density 3D NOR. That does not show that existing serial NOR portfolios have generally moved to 3D arrays, nor does it predict the price or lead time of a particular device. For production, use the exact part's datasheet, product status and application qualification as the decision points.
Supplier names matter less than the job the memory performs #
NOR is sold in more than one form. Microchip, Infineon, Macronix, Winbond and GigaDevice offer product lines aimed at different capacities, interfaces and operating conditions. Serial SPI NOR is common for board-level boot and firmware storage; parallel NOR remains relevant where a system uses the corresponding bus and access model. A supplier name is not a product family, and a product family is not a complete ordering code. Parts of equal capacity can differ in supply voltage, package, pin assignment, read commands or protection features.
On an MCU or industrial-control board, external NOR may store a boot program, application firmware or a modest amount of parameters. Another board may use only its MCU's internal Flash. A Linux-capable platform might keep an early boot stage in NOR and place the operating system and files in eMMC or another high-capacity device. A different processor might boot directly from managed storage and need no separate NOR. The host's boot documentation determines the possible paths; the equipment category alone does not.
Automotive use brings additional system checks. Long-term availability, operating temperature, diagnostics expected by the functional-safety process and recovery after an interrupted update can all affect qualification. An AEC-Q100 device still needs verification of its grade, package, retention conditions and vehicle-program requirements. Industrial equipment may put particular weight on long service life, reliable repeated power-up and an update process that can recover in the field. Large volumes of photos, video or continuous logs in a consumer device usually belong on a different storage path. Increasing NOR capacity does not turn it into the natural choice for high-volume writes.
Those applications explain why the NOR/NAND distinction cannot be reduced to “fast versus slow.” A system can use both because the small boot path and the large data store do different jobs. The choice of one, both or neither follows from the software and host architecture.
Turn the architecture into an exact device choice #
Start with the host's supported boot path. Then verify capacity, supply voltage, package and pinout; SPI, QSPI or OSPI commands; address width; the highest usable clock mode; page and erase-region layout; write times; endurance; and retention conditions. If the product uses secure boot, check how write protection, identity or security regions work with the host's trust chain. Similar feature names do not guarantee compatible commands or an identical qualification procedure.
When an existing board has already qualified one NOR device, changing its supplier or suffix calls for a comparison of the complete ordering codes and boot-read commands. Test cold boot, recovery after abnormal power loss, firmware update and the relevant temperature limits on the target hardware. A datasheet comparison can narrow the candidate list, but it cannot substitute for the interactions among the boot ROM, controller configuration, board and software.
NOR's value is predictable access to a comparatively small body of important code and data. Whether the system can execute from it, how many images it can retain and how often it can be updated are decided together by the host, firmware layout and exact Flash device.
Key references #
- Microchip, Getting Started With SuperFlash Technology
- ST, AN5188 application note on external memory code execution
- Infineon, S25FL256LAGBHV020 product information
- Macronix, 2024 Annual Report