AMD Xilinx Spartan-6 Ordering Codes Guide

AMD's official Spartan-6 ordering figure uses XC6SLX100T-2FGG676C as its complete example. Read it as XC6SLX100T | -2 | FG | G | 676 | C: device type, speed grade, package type, Pb-free indicator, pin count and temperature range. Every character belongs on the RFQ and purchase order.

That compact string also marks the limits of a safe substitution. LX and LXT are different pinout families, the extra G changes the package material designation, and 484 or 676 alone does not identify a footprint. For a mature Spartan-6 design, preserving the full OPN is usually less risky than reconstructing it from a partial BOM description.

Open the full-size Spartan-6 ordering diagram and zoom.

Decode XC6SLX100T-2FGG676C #

DS160 treats XC6SLX100T as one device-type field rather than inviting buyers to decode every character independently. Its device table distinguishes logic-focused LX members—LX4, LX9, LX16, LX25, LX45, LX75, LX100 and LX150—from transceiver-equipped LXT members—LX25T through LX150T. The worked device is therefore an LXT part, and UG385 states that LX and LXT pinouts are not compatible even when a package designator looks the same.

Package and Pb-free characters stay together #

UG385 explains the material rule directly: a Pb-free package adds an extra G to the package code. Thus FG676 is the leaded form and FGG676 is the Pb-free form; FT256 becomes FTG256. AMD writes shared mechanical references as FG(G)676 or FT(G)256, with the parenthesized G showing the optional material character.

For the official example, FG is a 1.00 mm-pitch fine-pitch BGA, G is the Pb-free indicator and 676 is the pin count. UG385 lists that package at 27 × 27 mm. Do not reduce FGG676 to “676-ball BGA”: CS(G)484 and FG(G)484 both use 484 positions but have different body sizes, pitches and pin maps.

The leaded and Pb-free versions are identical in pinout, size and thermal characteristics according to UG385. That supports a footprint comparison, but the material change still belongs in assembly-process, RoHS and approved-vendor review rather than being silently normalized away.

Speed and temperature use ordering-specific spellings #

DS160 lists LX device grades -3, -3N, -2 and -1L for both commercial and industrial ranges. LXT omits -1L. In the orderable string, however, the low-power -1L grade is written -L1, and the no-MCB -3N grade is written -N3. Copying the data-sheet grade directly into an OPN can therefore produce a non-orderable string.

The final C covers 0°C to +85°C junction temperature, while I covers -40°C to +100°C. DS160 warns that not every device is offered in every speed and temperature grade. A proposed faster or wider-temperature variant remains a candidate until the exact device-package-grade combination is confirmed and the design is rerun through ISE timing, power and configuration checks.

The -N3 boundary is functional, not just performance binning: DS160 says Memory Controller Block functionality is not supported in that grade. Likewise, -L1 is LX-only and uses the lower-power 1.0 V core. Those changes cannot be approved from a distributor suffix comparison alone.

What can migrate and what forces board review #

UG385 gives a narrow starting point for density migration: LX devices supported in one particular package are pinout compatible with other LX devices in that package, and the same statement applies within LXT. The guide immediately adds the conditions that make a BOM swap an engineering task. Potential target densities can place no-connects on different balls, so a migration-ready board must avoid every ball that is NC in any planned device.

There are also device-specific exceptions. LX25 and LX25T do not support BPI configuration, and twelve pins in banks 1 and 3 use different BUFIO2 clocking regions from other densities in FT(G)256, CSG324 and FG(G)484. Larger members add encryption pins, while FG(G)676 and FG(G)900 devices can change the I/O-bank arrangement. These boundaries require the exact UG385 pin table and a fresh implementation, not only a matching package suffix.

AMD's current Spartan 6 product page now provides a migration flow toward newer cost-optimized FPGA and SoC families. That is useful lifecycle planning, but it is not a drop-in replacement table. The board team must choose the next family from I/O density, data rate, package size, DSP and processor requirements, then revalidate the complete design.

Procurement checklist #

• Put the complete XC6SLX100T-2FGG676C or production BOM OPN on the RFQ, PO and incoming-inspection record.
• Confirm LX versus LXT before comparing densities; the two pinout families are not interchangeable.
• Match the full package block, including the Pb-free G and pin count.
• Translate -1L to -L1 and -3N to -N3 only where the official device table offers those grades.
• Verify the exact device-package-grade row and the C or I temperature range.
• For density migration, compare every assigned ball, no-connect, bank, clock region, configuration pin, MCB and GTP connection in UG385.
• Rerun ISE implementation, timing, power and configuration checks for the proposed target.
• Specify tray or reel, lot, date code, moisture condition, traceability, quantity and delivery separately; those logistics are not encoded by DS160's OPN figure.

Conclusion #

Spartan-6 ordering codes are short, but none of their six official fields is disposable. Preserve the complete device, speed, FG/CS/FT package, Pb-free G, pin count and temperature letter. A same-family, same-package density can begin a pinout review; it does not waive no-connect, bank, clocking or hard-block checks. LX-to-LXT, cross-package and cross-generation changes require a board-level migration decision.

Official references #

• AMD Spartan-6 Family Overview DS160
• AMD Spartan-6 FPGA Data Sheet: DC and Switching Characteristics DS162
• AMD Spartan-6 FPGA Packaging and Pinouts Product Specification UG385
• AMD Spartan-6 FPGA PCB Design Guide UG393
• AMD Spartan 6 FPGA product page and migration resources