AMD Xilinx Zynq-7000 Ordering Codes Guide

AMD Xilinx DS190 uses XC7Z014S-2CLG484C as its Zynq-7000 ordering example. Read it as XC7Z014 | S | -2 | CL | G | 484 | C: part number, single-core indicator, speed grade, package type, Pb-free field, pin identifier and temperature range.

The complete orderable part number matters. A request shortened to XC7Z020 omits speed, package, material and temperature information, so it is not enough for a purchase order or substitution review.

Open the full-size Zynq-7000 ordering diagram and zoom.

Decode XC7Z014S-2CLG484C field by field #

The S field changes the processor architecture #

DS190 lists XC7Z007S, XC7Z012S and XC7Z014S as single-core ARM Cortex-A9 products. XC7Z010, XC7Z015, XC7Z020, XC7Z030, XC7Z035, XC7Z045 and XC7Z100 are dual-core devices. The S immediately after the device number is therefore a functional architecture field, not packaging text.

Removing S from XC7Z014S does not produce another valid version of the same device. Likewise, adding S to XC7Z020 does not create a single-core XC7Z020. If a shortage forces movement between members, software, boot behavior, processing resources, programmable logic, peripherals and package support all require a fresh design review.

Speed and temperature combinations are device-specific #

The ordering figure lists -3, -2, -1, -1L and -2L syntax, but Table 7 limits the grades actually offered for each device group. For XC7Z010, XC7Z015 and XC7Z020, commercial parts are listed at -1; extended parts at -2 and -3; and industrial parts at -1, -2 and -1L. A syntactically plausible combination can still be non-orderable.

Lower-power -1L and -2L also use the ordering forms -L1 and -L2. They are not spelling variants of ordinary -1 and -2 stock. Engineering must review the supported voltage, timing and power conditions before selecting them.

CLG484 is one package identity #

The diagram separates CL, G and 484 so each field can be decoded, but procurement should treat CLG484 as a complete package identity. DS190 lists CLG225, CLG400, CLG484 and CLG485 at 0.8 mm pitch. It lists FBG484, FBG676, FFG676, FFG900 and FFG1156 at 1.0 mm pitch, plus SBG485 for selected devices.

Changing CLG484 to FBG484 does not preserve the footprint merely because both include 484. Body size, pitch and ball map differ. Even within the CLG family, 225, 400, 484 and 485 identify different mechanical and electrical packages.

The G character must also be interpreted with the package family. DS190 defines G in CLG as RoHS 6/6, while G in SBG, FBG and FFG is RoHS 6/6 with Exemption 15. The same letter is not a universal material statement across every package.

Shortage substitution example #

When XC7Z020-1CLG484C is unavailable, XC7Z020-1CLG484I can be screened as an engineering alternate: the device, speed grade and CLG484 package remain the same, while the I grade extends the junction-temperature range from 0°C to +85°C to -40°C to +100°C. DS190 Table 7 lists -1 in both commercial and industrial classes for XC7Z020.

This is a one-way environmental upgrade candidate, not automatic approval. Industrial stock may cost more. Engineering still needs to confirm that the exact OPN is orderable, compare the current package pinout, rerun implementation and timing checks, review power, and update the approved BOM. A C-grade part cannot replace an I-grade requirement in the reverse direction.

Do not apply the same logic to XC7Z020-2CLG484C: DS190 does not list -2 commercial for XC7Z020. Replacement searches must start from official device-grade tables rather than constructing an OPN from familiar-looking fields.

Pin-to-pin boundaries #

The same complete package is necessary for the closest mechanical candidate, but it is not sufficient to prove pin-to-pin compatibility across different Zynq members. DS190 Tables 2 and 3 show that package availability, PS I/O, SelectIO and GTP or GTX resources vary by device.

AMD explicitly notes one special relationship: Z-7012S and Z-7015 in CLG485 and Z-7030 in SBG485 are pin-to-pin compatible. That documented exception demonstrates why a general visual package match is not enough. For every proposed alternate, use the current AMD package and pinout files to compare power, DDR, MIO, configuration, JTAG, transceiver, XADC and user-I/O balls, then rebuild the project for the exact target in Vivado.

Procurement checklist #

1. Copy the complete OPN from the released BOM, including S where present. 2. Confirm the device is single-core or dual-core; do not treat S as optional. 3. Verify the exact speed and temperature combination in DS190 Table 7. 4. Keep package type, Pb-free field and pin identifier together as one package identity. 5. Compare body size, pitch and device-package availability before checking ball assignments. 6. Use the current AMD package pinout file for every power, PS, PL, DDR and configuration ball. 7. Rebuild the design for the proposed target and review timing, power and software impact. 8. Confirm lifecycle, traceability, date code, moisture condition, packing medium, quantity, lead time and price.

Conclusion #

A Zynq-7000 OPN is complete only when its device, core indicator, speed, package, material, pin and temperature fields are known. Same-device industrial stock in the identical CLG484 package can be a practical shortage candidate for a commercial part, but official grade availability, package pinout and project-specific validation still decide whether it can be used.

Official references #

• AMD Xilinx Zynq-7000 SoC Data Sheet: Overview DS190
• AMD Zynq-7000 SoC product overview
• AMD Zynq-7000 SoC Technical Reference Manual UG585
• AMD board and system design package-pinout resources