XC2VE3558-1MSESBVA1444 is AMD's current official example for reading a Versal ordering code. It identifies a commercial Gen 2 Versal AI Edge device with value index 3558, -1 speed, mid-voltage and standard-static choices, extended temperature grade, and the SBVA1444 package construction and footprint fields. AMD labels it as an example and notes that mechanical samples are available, so use it to understand the syntax rather than as proof of production availability.
The procurement rule is to preserve the complete string. A change in the first device fields can select another generation, series or resource tier. A change in the middle grade fields can alter speed, voltage, static-power screening or temperature range. A change in the final package fields can alter pitch, lid construction, footprint, mechanical outline or ballout.
Open the full-size Versal ordering diagram and zoom.
Decode XC2VE3558-1MSESBVA1444 field by field #
| Field | Example | Official meaning | Procurement check |
|---|---|---|---|
| Commercial prefix | XC | Commercial device prefix in the DS950 example | Do not silently replace it with another qualification prefix. |
| Generation | 2 | Gen 2 | DS950 limits this character to AI Edge Gen 2, Prime Gen 2 and Premium Gen 2 devices. |
| Architecture | V | Versal | Keep this field with the following series code. |
| Series | E | AI Edge Series | C is AI Core, M is Prime, P is Premium, H is HBM and R is RF. |
| Value index | 3558 | Device resource identifier | It is a silicon member, not a package or speed bin. |
| Speed | -1 | Slowest of the -1, -2 and -3 labels in the generic decoder | Only combinations listed for the selected series and device are orderable. |
| Voltage | M | Mid-voltage option | L is low and H is high; confirm the data-sheet operating point. |
| Static screen | S | Standard static screening | L denotes low-static screening. |
| Temperature | E | Extended grade | I denotes industrial grade; the exact junction limits and grade combination come from DS950. |
| Ball pitch | S | 0.8 mm | L is 1.0 mm, V is 0.92 mm with LSC, N is 0.92 mm without LSC, and J is 0.65 mm. |
| Lid | B | Lidless, without stiffener ring | Other documented codes cover lidded, overhang, stiffener-ring and memory-on-package constructions. |
| RoHS 6 | V | Pb-free ball code | DS950 also states that every package uses Pb-free bumps. |
| Footprint | A1444 | Package designator plus BGA pin count | Match the complete footprint identifier before beginning a migration review. |
The code is intentionally dense. MSE is not one grade: M is voltage, S is static screening and E is temperature. SBVA1444 is not a single decorative package suffix either: S gives pitch, B gives lid construction, V gives the RoHS ball code and A1444 gives the footprint identifier.
Series and generation are architectural boundaries #
The current DS950 overview covers AI Edge, AI Core, Prime, Premium, HBM and RF series. The series letter therefore selects a product architecture and resource set, not a sales tier. AI engines, processing systems, memory controllers, transceiver types, integrated hard IP and package choices vary across these series.
The leading 2 is equally specific. AMD's Figure 3 says it is present only for AI Edge Series Gen 2, Prime Series Gen 2 and Premium Series Gen 2. Do not add it to a first-generation OPN or remove it from a Gen 2 device because the remaining digits look similar. Such a change crosses a device-generation boundary and requires a new implementation, power plan, pin review and qualification.
Speed, voltage, static screen and temperature form one combination #
DS950 Table 29 publishes valid speed, voltage, static-power and temperature combinations by series and device. The generic decoder defines -1 as slowest, -2 as mid and -3 as fastest, but that ranking does not make every grade available for every device.
The voltage letter and static-screen letter must travel with the speed and temperature fields. For example, -2MSE and -2LLI describe different voltage, static-power and temperature choices. A buyer cannot approve one from the visible -2 alone. Confirm that the complete grade string is listed for the exact device, then recheck timing, rail voltage, power, thermal assumptions and customer qualification.
DS950 defines E as extended temperature, 0°C to +100°C, and I as industrial, -40°C to +110°C for the listed current combinations. Its note adds that operation at +110°C is limited to 3% of device lifetime for applicable extended and industrial combinations. That condition belongs in the qualification record; it is not erased by calling I a wider grade.
The package string carries four independent decisions #
The final package string combines ball pitch, lid construction, RoHS ball code and footprint. The pitch codes alone span 0.65, 0.8, 0.92 and 1.0 mm choices. Lid codes distinguish lidless, lidded, stiffener-ring, overhang and memory-on-package constructions. Those fields affect land pattern, assembly, heat-sink contact, keep-out and inspection.
AMD's current packaging manual AM013 is the package and pinout authority. DS950's device-package tables then show which package choices and maximum I/O counts apply to each device. A matching ball count is not enough; the package designator letter inside the footprint identifier remains significant.
Package migration is a controlled engineering task #
AMD's current UG863 migration guidance says that two packages with the same footprint identifier code are footprint compatible. The identifier combines the package designator and BGA pin count, such as A2197, C1760 or D1760. That establishes a mechanical starting point, not automatic electrical compatibility.
The same guidance requires checks for XPIO, HDIO and transceiver counts, added power rails, bank and GT-quad differences, reference pins, decoupling, package flight time and mechanical outline. Its example shows that VM1502 in a C1760 package can migrate only within the C1760 footprint group, while a D1760 package with the same 1760 ball count is a different footprint group. It also shows packages that share a BGA footprint while their body dimensions or overhang differ.
| Proposed change | Sourcing assessment |
|---|---|
| Same device, package and a currently listed faster grade | Engineering-screened candidate after timing, voltage, power and thermal review |
| E to I with the same device, package and supported grade string | Qualification change; confirm lifetime and temperature requirements |
| First generation to Gen 2 | Architecture migration; new design and validation required |
| E, C, M, P, H or R series letter change | Different Versal series; not a purchasing substitution |
| Same ball count but different footprint designator | Different footprint group; not pin-to-pin by ball count |
| Same footprint identifier across two devices | Mechanical starting point only; complete electrical and pin migration review still required |
| Pitch, lid or overhang change | Assembly, PCB and thermal review required |
Procurement checklist #
- Put the full AMD ordering code on the RFQ, purchase order and incoming-inspection record.
- Confirm the generation character is present only for a supported Gen 2 series.
- Match the Versal series letter and complete value index.
- Treat speed, voltage, static-screen and temperature letters as one validated combination.
- Match pitch, lid, RoHS and the complete footprint identifier.
- Use DS950 for current device-package and grade availability, AM013 for pinout and package details, and UG863 for migration checks.
- Require engineering approval for any silicon, generation, package, voltage or qualification change.
- Confirm packing method, MSL condition, tray or reel state, date code, lot traceability and delivery schedule before release.
Conclusion #
A Versal OPN is a compact engineering contract. The left side selects generation, series and device value; the middle fixes performance, voltage, static-power and temperature choices; the right side fixes package construction and footprint. Preserve all three groups in sourcing, and treat even a same-footprint device as a migration candidate until the current AMD pin, power, implementation and mechanical checks are complete.
Official references #
- AMD Versal Architecture and Product Data Sheet: Overview DS950
- AMD DS950 Versal device ordering information
- AMD Versal Adaptive SoC Packaging and Pinouts Architecture Manual AM013
- AMD AM013 package and pinout overview
- AMD Versal Adaptive SoC PCB Design User Guide UG863
- AMD UG863 footprint compatibility between Versal packages
- AMD Versal package-device pinout files
Need stock, date-code or package confirmation?
Send the part number, quantity, target date code and packaging requirements. LimChip will check available lots and RFQ details before you place the order.
Send RFQ