AMD Zynq UltraScale+ RFSoC Ordering Codes Guide

AMD DS889 uses XCZU25DR-1FFVE1156E as its Zynq UltraScale+ RFSoC ordering example. Read it as XC | ZU | 25 | D | R | -1 | F | F | V | E1156 | E: commercial prefix, product family, value index, processor system, RF engine, speed grade, package technology, lid option, material, footprint identifier and temperature grade.

A purchase request shortened to ZU25DR omits the timing, package construction, footprint and environmental grade. Those missing fields decide whether stock can be assembled onto the board and qualified for the intended operating conditions.

Open the full-size Zynq UltraScale+ RFSoC ordering diagram and zoom.

Decode XCZU25DR-1FFVE1156E field by field #

DR identifies the RFSoC architecture #

The adjacent D and R characters describe two different functions. D identifies the quad-core Arm Cortex-A53 application-processing system with dual Cortex-R5F real-time processors. R identifies the RF signal engine. Together they distinguish a Zynq UltraScale+ RFSoC from CG, EG and EV MPSoC members.

Changing XCZU25DR to a similarly sized EG or EV device is not a suffix substitution. It changes the converter architecture, hard blocks, software target and board requirements. Even movement between RFSoC value indices can change RF-ADC and RF-DAC counts and rates, SD-FEC resources, transceivers, I/O and supported packages.

Speed, temperature and voltage are linked #

DS889 lists -1, -L1, -2 and -L2 ordering forms. The L forms are ordering codes for the low-power -1L and -2L grades. DS926 adds the operating-voltage boundary: selected low-power devices can operate at 0.72 V, while some combinations support 0.85 V or 0.72 V under stated conditions.

Do not build an alternate by changing only the printed speed text. Check the current device row in DS926 for the exact speed, temperature and VCCINT combination, then rerun timing and power analysis. The fastest available grade also varies by device group; a syntactically plausible OPN is not proof that AMD offers it.

RFSoC DFE members such as XCZU65DR and XCZU67DR have a narrower published ordering range than many Gen 1–3 devices. Their industrial-only availability in the official tables is a reason to keep DFE sourcing separate from ordinary RFSoC assumptions.

FFVE1156 is one package identity #

Although the ordering figure separates F, F, V and E1156, procurement should control FFVE1156 as a complete package identity. The first F defines 1.0 mm flip-chip technology, the second F identifies the lid, V states RoHS 6/6 and E1156 identifies the footprint.

The same 1156 pin count does not establish the same land pattern or ballout when another package designator is used. A change to a lidless construction also affects mechanical height, heatsink contact and assembly handling even if the footprint were otherwise supported.

Use UG1075 and the current AMD package files to compare power, PS DDR, boot, configuration, JTAG, RF converter supplies and clocks, transceiver reference clocks, PL banks and no-connect balls. RF converter and analog supply pins make visual package similarity especially unsafe as a compatibility test.

Shortage substitution example #

If XCZU25DR-1FFVE1156E is unavailable, XCZU25DR-1FFVE1156I can be screened as an environmental-grade alternate because the device, speed and FFVE1156 package remain fixed while the temperature grade changes. DS889 lists both -1E and -1I for the ZU21DR through ZU29DR group.

That comparison is not automatic approval. Industrial inventory may cost more, and engineering must confirm the current orderable OPN, DS926 electrical limits, package data, Vivado target, RF clocking, converter calibration, timing, power and thermal performance. The reverse move from I to E cannot satisfy an industrial requirement.

Do not extend this logic to a different value index or to an OPN ending in another package designator. Changes in converter channels, sampling performance, SD-FEC, GT resources or ball assignments require a redesign and validation plan.

Pin-to-pin and migration boundary #

The closest replacement candidate keeps all fields identical except for a documented upward temperature or performance grade. Same family plus same ball count is not sufficient.

For every cross-device proposal, compare the current product-selection guide and package files first. Confirm the exact RF-ADC/RF-DAC resources, clock inputs, analog supply pins, GT resources, PL banks and PS interfaces. Rebuild the Vivado design for the proposed part, review timing and power, regenerate software and boot artifacts, and validate the RF data-converter configuration on hardware before releasing production purchasing.

Procurement checklist #

1. Copy the complete OPN from the approved BOM, including DR and all package characters. 2. Confirm the value index provides the required RF converters, rates, SD-FEC, logic and transceivers. 3. Verify the speed, temperature and VCCINT combination in current AMD tables. 4. Treat low-power -L1 and -L2 as distinct operating grades. 5. Keep package technology, lid, material and footprint together as one package identity. 6. Compare the current package file ball by ball, including analog and RF clock supplies. 7. Rebuild Vivado and validate timing, power, software, RF configuration and thermal behavior. 8. Confirm lifecycle, traceability, date code, moisture condition, packing medium, quantity, lead time and price.

Conclusion #

XCZU25DR-1FFVE1156E is complete only when all eleven fields are preserved. An industrial version in the identical device, speed and package can be a useful shortage candidate for an extended-grade requirement, but official orderability, voltage limits, pinout and complete RF system validation still decide whether it can be approved.

Official references #

• AMD Zynq UltraScale+ RFSoC Data Sheet: Overview DS889
• AMD Zynq UltraScale+ RFSoC DC and AC Switching Characteristics DS926
• AMD Zynq UltraScale+ Device Packaging and Pinouts UG1075
• AMD Zynq UltraScale+ RFSoC product page
• AMD Zynq UltraScale+ RFSoC Product Selection Guide XMP105