AMD Spartan UltraScale+ Ordering Codes Guide

XCSU35P-2SBVB625E specifies a Spartan UltraScale+ SU35P FPGA, -2 speed grade, 625-ball SBVB625 package and extended junction-temperature range. AMD explicitly identifies this device on its SCU35 evaluation-kit page. The entire string matters: SU35P identifies the silicon, while SBVB625 and E constrain the package and operating range independently.

For purchasing, decode the OPN first, then check whether that exact device, package and grade is supported. A family product table establishes the portfolio; it does not establish production status or immediate availability for every combination. This guide uses AMD documents current when reviewed on September 13, 2026.

Read the complete Spartan UltraScale+ ordering code #

DS890 v4.10 Figure 4 defines the shared UltraScale+ FPGA syntax. Applied to AMD's SCU35 device, the fields read as follows.

The two occurrences of B perform different jobs. The first describes construction; the B immediately before 625 belongs to the footprint identifier. Likewise, 625 counts package balls, not user I/O. DS890 lists 252 HDIO plus 52 HPIO for SU35P in SBVB625, so its user-I/O total is 304.

The official shared diagram uses XC2KU050P-1SSVA1440E, a Kintex UltraScale+ Gen 2 example. Its extra 2 after XC applies only to that family; Spartan does not gain a Gen 2 field by analogy. The figure also includes speed and package options for other UltraScale+ families. Use its field definitions together with the Spartan-specific tables, rather than treating every illustrated option as an available Spartan order.

Nine device members, different resource boundaries #

DS890 Table 3 lists SU10P, SU25P, SU35P, SU45P, SU60P, SU65P, SU100P, SU150P and SU200P. The value index is a device identifier, not an exact logic-cell count or a promise of compatibility.

The first three members have no GTH transceivers. SU45P through SU100P have four at the device level; SU150P and SU200P have eight. Package bonding can expose fewer, so a resource maximum is not an interface guarantee for every package.

SU60P and SU65P illustrate why a nearby number is insufficient for alternate selection. Both list 65,625 system logic cells, but SU65P adds two integrated memory controllers and XP5IO resources that SU60P lacks. The integrated controllers also appear in SU100P, SU150P and SU200P. A design using those resources cannot be qualified by matching logic-cell count alone.

The family remains distinct from the devices covered in our Artix UltraScale+ ordering guide. Similar syntax does not transfer package options, configuration behavior or implementation support between families.

Package letters, pitch and body size #

For the worked device, SBVB625 is a bare-die flip-chip BGA with 0.8 mm pitch and a 21 × 21 mm body, documented in UG575. Other Spartan package constructions include chipscale molded packages: C means chipscale with 0.5 mm pitch and M means molded in DS890's decoder. These are independent from V, the material code.

Both packages above have 529 balls. DS890 Table 4 gives CMVA529 a 12 × 12 mm body and SBVC529 a 19 × 19 mm body; their pitch and footprint identifiers also differ. The original illustration compares body dimensions only. A529 and C529 must not be reduced to the number 529 when screening a BOM.

Package choice can also change interface limits. DS890 Table 3 caps GTH data rates at 12.5 Gb/s in CMVB529 and CMVE529. Do not apply a headline transceiver rate to every package. Confirm the exact device-package row, exposed transceivers, bank types and interface specification before layout or purchasing approval.

Speed, low-power spelling and temperature #

DS930 v1.3 lists -2 and -1 speed grades. The family combinations in DS890 Table 33 are -2E, -2I, -1E, -1I and -1LI. The standard nominal VCCINT is 0.85 V; supported -1LI devices can operate at 0.85 V or 0.72 V, with reduced performance at the lower voltage.

The low-power ordering field is -L1, while the data-sheet speed designation is -1L. Figure 4 explicitly distinguishes the two spellings. DS930 further calls the 0.72 V selection -1LV in Vivado, versus -1L at 0.85 V. These tool labels are not suffixes to append to an RFQ. Preserve the manufacturer's complete orderable string.

At 0.85 V, DS930 says the -1LI speed specification matches -1I. At 0.72 V, timing and power change. A proposed low-power alternate therefore needs the correct voltage configuration and timing analysis; matching the digit 1 is insufficient.

E means a junction-temperature range of 0°C to +100°C, and I means -40°C to +100°C. These are silicon junction limits, not ambient-temperature guarantees. Neither the XC prefix nor the industrial I suffix establishes automotive qualification. Do not invent an XA or military variant by replacing letters in an XC order.

Production status is a separate check #

In DS930 v1.3 Table 30, dated June 2, 2026, SU10P, SU25P and SU35P appear under Production; SU45P, SU60P, SU65P, SU100P, SU150P and SU200P appear under Advance. Table 31 lists Vivado 2025.1 and speed specification v1.11 as the minimum production release for the first three, with blank entries for the other six.

These are the statuses in that dated document, not a claim that no later release can exist. Before a production commitment, request current AMD confirmation for the exact device and grade when the table is incomplete or newer release evidence is offered. A board listing, an engineering sample or a seller's stock description does not independently establish a production-qualified alternate.

Figure 4 does not define a universal tray/reel suffix for this family. Keep shipment packaging, lot/date information and moisture handling as separate order requirements. Any extra engineering-sample or special-order marking needs documentation for that exact device; do not silently remove it to match a standard OPN.

Footprint compatibility and pin-to-pin limits #

UG575 v1.22 Table 1-8 lists SU10P, SU25P and SU35P together for A361, A529 and B625. This supplies a documented starting point for migration among those device/package groups. It does not make their resources or bitstreams interchangeable.

UG575 explicitly warns that footprint compatibility does not necessarily mean every pin functions identically. Compare the exact package pinout files, including No Connect entries, power and configuration pins, bank supplies, clock-capable pins and the signals used by the design. Then retarget the implementation and review timing, power and configuration requirements. A common ball pattern alone is not a board-level approval.

The documents also differ in coverage: DS890's May 2026 package matrix includes newer combinations beyond those enumerated in UG575's March 2026 compatibility table. Do not extend the older table's explicit SU10P/SU25P/SU35P B625 grouping to another member without the corresponding current pinout and migration evidence.

Release the order with the right evidence #

• Match the full manufacturer OPN, including its speed spelling and final temperature letter.
• Confirm the device-package pair and body dimensions against the current package documents.
• Check dated production status and the supported Vivado/voltage configuration.
• Require engineering approval for device, package, voltage or qualification changes; retain the pinout comparison.
• Record packing, moisture condition, acceptable lot/date range and traceability separately from the OPN.

XCSU35P-2SBVB625E is a useful anchor because AMD documents the complete device in an actual evaluation kit. Its decode is only the first step: the correct procurement decision combines the complete ordering string, supported grade, production evidence and package-specific engineering review. When a proposed alternative changes any of those, resolve the difference before releasing the purchase order.

Official references #

• AMD Spartan UltraScale+ FPGA portfolio and device table
• AMD SCU35 evaluation kit — featured XCSU35P-2SBVB625E device
• DS890 v4.10 — UltraScale architecture overview, Tables 3, 4 and 33, Figure 4
• DS930 v1.3 — Spartan UltraScale+ DC and AC switching characteristics
• UG575 v1.22 — packaging, footprint compatibility and pinouts