AMD Spartan UltraScale+ Ordering Codes Guide

XCSU35P-2SBVB625E is a current, manufacturer-documented Spartan UltraScale+ orderable part number: AMD identifies it as the FPGA fitted to the SCU35 evaluation board. Read from left to right, the code selects a commercial Spartan UltraScale+ SU35P device, -2 speed grade, SBVB625 package construction and footprint, and extended-temperature grade.

The purchasing rule is to preserve the complete string. SU35P alone does not identify speed, mechanical package, ball map or temperature range. SBVB625 alone does not prove that another Spartan UltraScale+ device is electrically interchangeable. Any proposed alternate must exist in AMD's current device-package tables and then pass implementation, power, pin and qualification review.

Open the full-size Spartan UltraScale+ ordering diagram and zoom.

Decode XCSU35P-2SBVB625E field by field #

The final SBVB625 block contains four purchasing decisions. S defines the package-technology pitch, B defines the lid construction, V defines the material code, and B625 identifies the footprint variant and ball count. A distributor description that shortens this to “625-ball BGA” loses information needed for PCB, thermal and compliance review.

The official ordering syntax ends with the temperature field. It does not encode tray, reel, moisture-barrier condition or shipment lot in this OPN. Record those logistics requirements separately on the purchase order rather than inventing an ordering-code suffix.

Device value changes alter the platform #

AMD's current product table spans SU10P, SU25P, SU35P, SU45P, SU60P, SU65P, SU100P, SU150P and SU200P. The number is not merely a density label: connectivity and hard blocks change across the range.

That split gives Spartan UltraScale+ a distinct sourcing decision from Artix UltraScale+. Moving from SU35P to SU45P does not simply add logic: it crosses into a group with high-speed transceivers and PCIe, while the headline maximum I/O count is lower. Moving to SU65P introduces integrated LPDDR4X/5 controllers and another package/resource envelope. Re-targeting the implementation is mandatory.

Speed, voltage and temperature must travel together #

DS930 version 1.3 states that Spartan UltraScale+ devices are available in -2 and -1 speed grades, with -2E and -2I providing the highest performance. It also documents selected -1LI devices that can run VCCINT at 0.85 V or 0.72 V. At 0.72 V, performance and both static and dynamic power are reduced.

This makes a same-device “faster grade” substitution an engineering screen, not an automatic purchasing upgrade. Confirm that AMD offers the exact device-package-grade combination, then rerun timing and power analysis at the intended VCCINT. DS930 also says that only selected speed grades and devices are available in each E or I temperature range.

SBVB625 is a mechanical and electrical constraint #

AMD's current selection guide identifies SBVB625 as a 21 × 21 mm, 0.8 mm-pitch, 625-ball option. The same guide's device-package table is the first check for whether a proposed device member exists in that footprint. DS930 separately names SBVB625 in package-specific electrical and assembly tables, so package behavior must not be inferred from ball count alone.

Other Spartan UltraScale+ packages include compact CMVA and CMVB options and larger SBV or NBV footprints. Changing to one of them changes the package code, body or ball map and therefore requires PCB and assembly review. Even when AMD lists two devices in the same footprint, compare the current UG575 pinout files and the exact power, configuration, I/O-bank and transceiver pins before describing a board as migration-ready.

Pin migration is not established by a shared family name #

AMD's UltraScale PCB guidance treats migration as a set of footprint, voltage, pin, memory-interface and package-flight-time checks. The product-selection matrix tells buyers which device-package combinations are offered; it is not a blanket pin-compatibility declaration.

For a proposed alternate, compare the complete package pinout in UG575, power rails, configuration pins, I/O bank types and voltages, clock inputs, transceiver quads, memory-controller pins and mechanical outline. Then select the exact target device in Vivado and rerun implementation. A shared SBVB625 label can establish a package starting point, but only the device-specific pin and implementation evidence establishes whether a particular board migration is acceptable.

Procurement checklist #

• Put the full XCSU35P-2SBVB625E string on the RFQ, purchase order and incoming-inspection record.
• Match XC, SU35P and the P architecture suffix before reviewing grade options.
• Treat -2 and E as a validated combination, not independent decorative characters.
• Match all four package positions: S, B, V and B625.
• Confirm the exact device-package combination in the current AMD selection guide.
• Recheck timing, VCCINT, power and thermal limits for any speed or temperature alternate.
• Use UG575 pinout files and Vivado for every device or footprint migration.
• Specify packing method, MSL condition, date code, lot traceability and delivery schedule separately.

Conclusion #

XCSU35P-2SBVB625E is a compact contract for silicon, performance, mechanical package, material and temperature. Keep SU35P and SBVB625 fixed before screening grade alternatives. Treat any value-index or package change as a migration project, because Spartan UltraScale+ resource groups differ in I/O, transceivers, memory controllers and PCIe even when the family name stays the same.

Official references #

• AMD Spartan UltraScale+ FPGA product page and current product table
• AMD UltraScale Architecture and Product Data Sheet: Overview DS890
• AMD Spartan UltraScale+ FPGA Data Sheet DS930 summary
• AMD UltraScale+ FPGA product selection guide
• AMD SCU35 board guide: XCSU35P-2SBVB625E device
• AMD UltraScale and UltraScale+ packaging and pinouts UG575
• AMD UltraScale PCB design guide UG583 migration scenarios