AMD Zynq UltraScale+ MPSoC Ordering Codes Guide

AMD DS891 uses XCZU7EV-1FFVC1156E as its Zynq UltraScale+ MPSoC ordering example. Read it as XC | ZU | 7 | E | V | -1 | F | F | V | C1156 | E: product prefix, family, value index, processor system, engine type, speed grade, package technology, lid option, material, footprint identifier and temperature grade.

Every field belongs on the purchase order. A shortened request such as ZU7EV identifies a device class, but it does not identify the performance, package construction, footprint or environmental grade that manufacturing must receive.

Open the full-size Zynq UltraScale+ MPSoC ordering diagram and zoom.

Decode XCZU7EV-1FFVC1156E field by field #

CG, EG and EV are architectural choices #

The letters following the value index are not optional marketing suffixes. AMD describes CG devices as the dual-core entry point, EG devices as quad-core products with a GPU, and EV devices as adding an integrated H.264/H.265 video codec to the quad-core/GPU platform.

For the worked example, E is the processor-system identifier and V is the video engine type. Changing XCZU7EV to XCZU7EG removes the video-engine designation; changing it to a CG member changes the application-processor configuration. Those moves affect software, boot images, programmable-logic resources, peripherals and potentially board support. They are redesign candidates, not stock substitutions.

Speed and low-power codes must stay exact #

DS891 shows -1, -L1, -2, -L2 and -3 ordering forms. Its note explains that -L1 and -L2 are the ordering codes for the -1L and -2L speed grades. Procurement should preserve the complete spelling because timing and power assumptions are tied to the selected grade.

A faster grade can sometimes be screened for a slower-grade shortage when the complete device and package remain fixed, but engineering must rerun implementation and timing for the exact target. Lower-power parts require their published operating conditions; they should not be treated as ordinary -1 or -2 inventory with an extra letter.

FFVC1156 is one package identity #

The diagram separates package technology, lid option, material and footprint so each character can be decoded. For footprint control, treat FFVC1156 as one package identity.

Changing the first F to S changes ball pitch from 1.0 mm to 0.8 mm. Changing it to U selects the 0.5 mm InFO construction. Changing the second F changes the lid or die presentation. Even when two OPNs end in the same numeric pin count, those construction fields can change the mechanical interface, assembly process and thermal solution.

UG1075 is the package and pinout authority for package dimensions and ball assignments. Confirm that the proposed device is offered in the exact package, then compare power, PS, DDR, configuration, transceiver and programmable-logic balls. A matching number such as 1156 alone never proves pin compatibility.

Shortage substitution example #

When XCZU7EV-1FFVC1156E is unavailable, an XCZU7EV-1FFVC1156I can be considered only after AMD's current speed and temperature tables confirm that exact I-grade combination is orderable. The device, architecture, speed and FFVC1156 package are held constant while the environmental grade changes.

This is a screening path, not an automatic pin-to-pin approval. Industrial inventory may cost more and can have different availability. Engineering still needs the current DS925 operating limits, the UG1075 pin data, a Vivado build for the exact OPN, power and thermal review, and an approved BOM change. The reverse move from I to E cannot satisfy an industrial-temperature requirement.

Do not use the same reasoning to replace XCZU7EV with XCZU7EG, or FFVC1156 with a package that merely has 1156 balls. Architecture and package-construction changes cross the safe boundary for a procurement-only substitution.

Pin-to-pin replacement boundary #

The closest candidate keeps all eleven fields identical except for a documented upward environmental or performance grade. Even then, pin compatibility is a device-package property, not an inference from similar text.

For any cross-device proposal, compare the current package files ball by ball. Check PS DDR and MIO, boot and configuration pins, JTAG, power rails, analog supplies, GTR/GTH resources, PL banks, voltage standards and no-connect requirements. Then rebuild the design, review timing and power, validate software and boot artifacts, and obtain engineering approval before purchasing production quantity.

Procurement checklist #

1. Copy the complete released OPN, including both architecture letters and every package character. 2. Confirm CG, EG or EV functionality against the system and software requirements. 3. Verify the exact value index and whether a T-enhanced member is involved. 4. Confirm the speed and temperature combination in current AMD data sheets. 5. Keep package technology, lid, material and footprint together as one package identity. 6. Compare UG1075 package support, dimensions, pitch and every relevant ball assignment. 7. Rebuild the Vivado project for the exact alternate and review timing, power and configuration. 8. Confirm lifecycle, traceability, date code, moisture condition, packing medium, quantity, lead time and price.

Conclusion #

XCZU7EV-1FFVC1156E is complete only when all eleven fields are preserved. Same-device industrial stock in the identical package can be a useful shortage candidate for extended-grade demand, but only after official orderability, electrical limits, pinout and project validation are confirmed. Architecture or package changes require a redesign review, not a purchasing shortcut.

Official references #

• AMD Zynq UltraScale+ MPSoC Data Sheet: Overview DS891
• AMD Zynq UltraScale+ MPSoC product page
• AMD Zynq UltraScale+ Device Packaging and Pinouts UG1075
• AMD Zynq UltraScale+ MPSoC DC and AC Switching Characteristics DS925