SAR vs Delta-Sigma vs Pipeline ADC — How to Read Resolution, Speed and ENOB Before You Choose

Why the number on the datasheet is not the number you get #

Every ADC datasheet leads with a resolution in bits: 16-bit, 24-bit, 14-bit. Buyers and firmware teams read that number as "the accuracy I will measure." It is not. The bit count is the converter's *label*, set by the digital output word width. What you actually recover from a real signal — the effective number of bits (ENOB) — depends on the architecture, the sampling rate, the input frequency and how much noise the front end hands the converter.

For a distributor and for an OEM designer, the practical question is never "how many bits does it claim?" It is "at the speed and input frequency my circuit runs, how many clean bits do I keep?" The three dominant precision ADC architectures — SAR, delta-sigma (Σ-Δ) and pipeline — answer that question very differently. This guide explains where each one lives and how to read the datasheet before committing to stock.

The three architectures at a glance #

The split is almost entirely about the throughput-versus-resolution trade. The faster you sample, the fewer clean bits you keep — and each architecture has its own curve.

SAR — convert on demand, zero latency #

A SAR converter performs one successive-approximation conversion per `CNV` pulse and returns the result on the next SPI frame. There is no pipeline delay: the sample you trigger is the sample you read. That makes SAR the natural choice for control loops, power-line monitoring and any system that multiplexes many channels and needs a result now.

A representative part is the AD7689 (Analog Devices): an 8-channel, 16-bit SAR at 250 kSPS. Its datasheet quotes SINAD of 92.5 dB at 20 kHz, which works out to roughly 15.1 ENOB — so a "16-bit" SAR actually delivers about 15 clean bits, with INL on the order of ±0.4 LSB typical. That gap between 16 and 15.1 is normal; it is noise and distortion, not a defect.

The multiplexer trap: with an 8-channel SAR at 250 kSPS, each channel switch must settle before the next conversion. Real per-channel rate is closer to 250 kSPS ÷ 8 once you account for acquisition time. Buyers sizing a scanner should budget the *per-channel* throughput, not the headline rate.

Delta-sigma — trade speed for resolution #

A Σ-Δ converter samples at a very high internal rate, then uses a noise-shaping loop and a digital decimation filter to push quantization noise out of the band of interest. The result is extraordinary resolution at low output rates — at the cost of latency from the filter and a hard ceiling on throughput.

The AD7192 (Analog Devices) is a clean example: a 24-bit Σ-Δ with an on-chip PGA, output data rate selectable from 4.7 Hz to 4.8 kSPS. Its datasheet states up to 22 noise-free bits at gain = 1, and 15.5 noise-free bits at 2.4 kSPS with gain = 128 (RMS noise 11 nV at 4.7 Hz, gain = 128). Note the wording: "noise-free bits" is the peak-to-peak, no-code-flicker figure, which is a few bits below the RMS-based "effective resolution." Either way, the *delivered* resolution is well under the 24-bit label, and it collapses as you raise the output rate or gain.

Σ-Δ parts such as the TI ADS1115 family (16-bit, I²C) bring this resolution down to a two-wire bus for thermocouples, bridges and slow industrial inputs. The lesson for buyers: a Σ-Δ "24-bit" part is only as good as the output rate and gain you actually run — and its filter needs time to settle after a channel change.

Pipeline — stage the conversion for gigasample rates #

Pipeline converters split each conversion across several cascaded stages, each resolving a few bits and passing a residue to the next. Throughput scales into the hundreds of MSPS and beyond, but each sample pays a fixed pipeline delay of several clock cycles before its word appears — and ENOB falls as input frequency rises.

The AD9689 (Analog Devices) is a dual 14-bit pipeline at 2.0/2.6 GSPS with a JESD204B serial interface. At 2.0 GSPS and a 900 MHz input it quotes SNR of 62.7 dBFS, which is about 10.1 ENOB. That is far below the 14-bit label — and it is expected, because pipeline converters are built for bandwidth and linearity, not for counting every quiet bit.

ENOB, SNR and SINAD — how to read the delivered bits #

ENOB is derived from the dynamic performance, not the digital word:

``` ENOB = (SINAD − 1.76) / 6.02 (use SNR when distortion is excluded) ```

SINAD folds signal, noise and harmonics together; SNR drops the harmonics. When a datasheet prints "16-bit" but SINAD is 92.5 dB, you do the math and get ~15.1 usable bits. Treat the bit label as the ceiling and the SINAD-derived ENOB as the floor you can actually design to.

The ENOB-versus-input-frequency trap #

High-speed converters do not hold their ENOB across the whole input range. As the analog input frequency climbs toward the converter's bandwidth, distortion rises and ENOB drops. This is visible directly in the AD9689 datasheet:

The 14-bit label is constant; the delivered bits fall from ~10 to ~8.5 as the input frequency moves up two octaves. Anyone specifying a pipeline ADC for a high-IF receiver must read the SNR/ENOB at *their* input frequency, not at the low-frequency test point on the front page.

Multiplexing and settling-time traps buyers miss #

• SAR scanners: per-channel rate ≈ sample rate ÷ channels, after acquisition-time

settling. A "250 kSPS, 8-channel" part is not eight streams at 250 kSPS.

• Σ-Δ scanners: the decimation filter has group delay. After switching channels,

wait the filter settling time (often tens to hundreds of output periods) before trusting the reading — or use a part with a zero-latency mode.

• Pipeline: usually driven by a track-and-hold front end; multiplexing is less

common, but the fixed latency still matters for closed-loop timing.

Interfaces: SPI, I²C, LVDS, JESD204B #

The architecture also decides the digital interface:

• SAR: SPI (separate `CNV`/`SCK`/`SDO`), sometimes I²C at low speed.
• Σ-Δ: SPI or I²C — the ADS1115 is the classic I²C example; the AD7192 is SPI.
• Pipeline: parallel CMOS/LVDS, or JESD204B serial at multiple gigabits per lane

for GSPS parts like the AD9689. JESD204B brings deterministic latency via SYSREF but adds clocking and logic complexity.

For an OEM, the interface choice can be as binding as the converter itself — JESD204B needs an FPGA transceiver; I²C needs almost nothing.

How to choose — a short decision path #

1. Sub-100 kSPS and you need the quietest possible reading (weigh scale, thermocouple, strain gauge, medical): pick Σ-Δ. Read the noise-free bits at your gain and output rate. 2. Multi-channel, moderate speed, low latency, true 16-bit (scanners, PLC inputs, battery systems): pick SAR. Budget per-channel throughput after settling. 3. Above ~100 MSPS, RF/IF sampling, comms or instrumentation bandwidth: pick pipeline with JESD204B. Read SNR/ENOB at your actual input frequency.

Related parts in stock #

The catalogue carries representative parts across all three architectures. Two are linked here as starting points for sourcing:

• AD7689BCPZRL7 — 16-bit, 8-channel SAR, 250 kSPS (multi-channel, low-latency

scanning).

• ADS1115IDGSR — 16-bit, I²C Σ-Δ (slow industrial and bridge inputs).

Higher-speed pipeline options (for example 14-bit GSPS JESD204B converters) are also available in the catalogue for direct RF sampling designs.

Conclusion #

Resolution on an ADC datasheet is a label, not a promise. SAR delivers low latency and true 16-bit at moderate speed; Σ-Δ trades throughput for the highest resolution; pipeline buys bandwidth and GSPS rates at the cost of fixed latency and falling ENOB with input frequency. Read the SINAD-derived ENOB at *your* speed and *your* input frequency, budget the multiplexer settling time, and match the interface to the host — then the bit count on the front page finally means something.