| Family / Architecture | Strat 10 2800, 14 nm Intel tri-gate (FinFET), Intel Hyperflore architecture with Hyper-Registers |
| Logic Elements | 2,753,000 logic elements (2,753 KLE), monolithic core fabric |
| Embedded Memory (M20K) | 229 Mbits (11,721 × 20K blocks) |
| Variable-Precision DSP | 11,520 × 18×19 multipliers with hard IEEE 754 floating-point |
| Hard Memory Controller | DDR4 up to 2666 Mbps, DDR3 up to 2133 Mbps |
| User I/O | 704 (F50 package) |
| Transceivers | Up to 96 channels (L-Tile); chip-to-chip up to 28.3 Gbps, backplane up to 12.5 Gbps |
| PCI Express | 4 hard PCIe Gen3 IP blocks (up to ×16) |
| PLLs | 32 fractional-synthesis fPLLs + 24 I/O PLLs |
| Speed Grade | Transceiver speed grade 2; FPGA fabric speed grade 2 |
| Temperature Grade | Extended (TJ = 0 °C to 100 °C) |
| Distributed Memory (MLAB) | 15 Mbits (23,796 MLABs) |
| Core Performance | Up to 1 GHz core fabric (Hyperfl ) |
| Power Option | SmartVID standard power (V) |
| Package / Orderable Variant | 2,397-ball Flip Chip BGA (F50), 50 × 50 mm, 1.00 mm pitch; exact suffix 1SG280LU2F50E2VG |
| Package Details | 2,397-ball Flip Chip BGA (F50), 50 × 50 mm, 1.00 mm pitch |
Altera