MAX96724FGTN/VY+T

制造商型号:
MAX96724FGTN/VY+T
制造商:
Analog Devices
产品类型:
Quad GMSL2 to CSI-2 Deserializer
系列:
MAX96724
封装:
TQFN-56
描述:
Quad GMSL2 to CSI-2 Deserializer

产品属性

属性数值
Supply VoltageVTERM 1.14 to 1.26 V; VDD18 1.7 to 1.9 V; VDD 0.95 to 1.05 V (1-V mode) or 1.14 to 1.26 V (1.2-V mode); VDDIO 1.7 to 3.6 V
Supply Current4 x 3-Gbps links, 2.45-Gbps PRBS24 payload/link, 1 x 4-lane D-PHY at 2500 Mbps/lane: VTERM 17 mA typical / 25 mA maximum at 1.26 V; VDD18 280 / 325 mA at 1.9 V; VDD 197 / 625 mA at 1.05 V; additional I/O current depends on load
Operating Temperature-40 to +105°C ambient; -40 to +125°C junction
Inputs4 independent GMSL2 / GMSL1 serial video inputs
Link RateGMSL2 up to 3 Gbps per forward link (F option); GMSL1 3.12 Gbps; reverse GMSL2 187.5 Mbps / GMSL1 1 Mbps
Output InterfaceCSI-2: 2 four-lane or 4 two-lane D-PHY ports, up to 2.5 Gbps/lane; C-PHY up to 5.7 Gbps-equivalent/lane; aggregation and replication
Virtual ChannelsUp to 16 CSI-2 virtual channels with D-PHY or 32 with C-PHY
Reference Clock25 MHz crystal / clock, +/-200 ppm; reference-over-reverse-channel distribution to serializers
Control2 local I2C ports up to 1 Mbps; configurable GPIO and link diagnostics
Package DetailsTQFN-SW-EP, T5688Y, 56 terminals; 8 x 8 mm body; 0.5 mm pitch; 0.75 mm nominal and 0.8 mm maximum height

产品描述

The F option limits each GMSL2 input to 3 Gbps while retaining four-camera aggregation and CSI-2 output routing. That limit must be checked against each camera payload before choosing it in place of the 6-Gbps member.

Flexible D-PHY and C-PHY outputs can combine or replicate incoming streams for a host processor. Virtual-channel mapping and the host lane configuration determine how the processor separates the cameras.

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