| Core / Architecture | Dual-core SHARC+ DSP; two SHARC+ cores; 32-bit fixed-point, 32/40/64-bit floating-point; cache + branch prediction |
| Clock Frequency | Up to 1000 MHz per core (−10 speed grade) |
| On-Chip Memory | 2 × 640 KB L1 SRAM (one per core); 2 MB L2 SRAM with ECC; 1.5 Mbit L2 boot ROM; 16-bit DDR3/DDR3L L3 interface |
| Processing Performance | Dual SHARC+ cores; enhanced FIR/IIR accelerators run to 1 GHz |
| Interfaces / Peripherals | 8 SPORTs, 2 S/PDIF, 8 ASRC pairs, PCGs, PDM mic inputs, DAI, 2 Quad SPI, Octal SPI, MLB, 6 I²C, 3 UART, 2 Link Ports, timers, watchdog, housekeeping ADC, GPIO, DDR3 DMC, thermal sensor, JTAG |
| Supply Voltage | Core VDD_INT/PLL 0.95–1.05 V; I/O 3.13–3.47 V; VDD_ANA/REF 1.71–1.89 V; VDD_DMC 1.34–1.575 V |
| Core Supply Current | Static 149 mA at VDD_INT 1.0 V, TJ 25 °C, plus per-core dynamic current (datasheet current equation) |
| Package Details | 400-ball BGA_ED (BP-400-3), 17 × 17 mm, 0.8 mm pitch |
Analog Devices
