| Core / Architecture | 28-bit/56-bit SigmaDSP core with integrated PLL; 50 MIPS |
| Clock / Processing | 50 MIPS; PLL input clock 8–27 MHz |
| On-Chip Memory | 1024×40-bit program RAM; 1024×32-bit parameter RAM; 4096-sample delay (~86 ms at 48 kHz) |
| ADC / DAC Resolution | 24-bit stereo ADC; 24-bit stereo DAC |
| Channels | Stereo ADC/DAC; 6 analog inputs (single-ended or differential); stereo digital mic; differential/single-ended stereo and mono headphone outputs |
| Audio Performance | ADC/DAC SNR >98 dB; THD+N ≥ −90 dB; ADC 99 dB A-weighted at 3.3 V |
| Sample Rate | 8 kHz to 96 kHz |
| Interfaces | I²S/TDM audio and digital microphone input; I²C and SPI control |
| Supply Voltage | AVDD/IOVDD 1.8–3.65 V; internal digital regulator |
| Operating Temperature | −40 °C to +85 °C |
| Package Details | 32-lead LFCSP (CP-32-4), 5 × 5 mm |
Analog Devices
