TI Power Designs for AMD-Xilinx FPGAs

TI has several FPGA power architectures, not one recipe #

Texas Instruments publishes power references that span AMD Spartan-7, Artix-7, Zynq-7000, Zynq UltraScale+, Virtex UltraScale+ and Versal platforms. They are useful because the official folders expose rail tables, schematics, bills of materials and test evidence. They are also easy to misuse: the references come from different design years, target different input buses and power domains, and do not all carry the same hardware-validation or lifecycle status.

The closest existing article is AMD-Xilinx FPGA Power Delivery: Design Guide. That guide compares ADI, Renesas, MPS and TI evidence across the whole power-delivery workflow. This article is separate because it answers a TI-specific release question: which official TI design applies to the exact FPGA, which regulator and configuration files belong in the BOM, and which older reference parts require a lifecycle or redesign gate.

Start with an exact device rather than a family label. XC7Z020-2CLG400I, XCZU3EG-1SBVA484E, XCZU9EG-2FFVB1156E and a Versal Prime device can all be described as AMD-Xilinx programmable devices, yet their rail count, current, sequence, reset ownership and memory power are different. The TI reference itself must also be named. “Use a TI PMIC” is not a reproducible engineering instruction.

The map is a LimChip original classification of current TI design folders. It shows where to begin the evidence review; it does not imply that every device inside a family is covered.

Freeze the AMD load case before selecting TI parts #

For UltraScale+ and Versal designs, AMD now identifies Power Design Manager (PDM) as the preferred estimation tool. The current 2026.1 release supports all UltraScale+ and Versal devices and exposes rail consolidation, sequence and dynamic-decoupling information. Xilinx Power Estimator remains the path for earlier families. In either tool, the output is only as reliable as the implemented clocks, utilization, transceiver count, I/O standards, processor load, memory interface and junction-temperature assumptions.

The TI design must be scaled from that file, not from a headline current. TIPA-010000, for example, calculates its proposed rails for XCZU9EG-2FFVB1156E with stated assumptions including 320 MHz clocks, 70% logic utilization, full Block RAM, UltraRAM and DSP utilization, and 4 A per used VCCO rail. Its 19 A core rail is therefore an input-specific estimate, not a universal XCZU9EG value.

Freeze these items before opening a regulator selector:

• complete FPGA or adaptive-SoC ordering code, package, speed and temperature grade;
• current PDM or XPE output plus its tool version and workload assumptions;
• required minimum-rail or full-power-domain scenario;
• input bus, surge range, hold-up and permitted intermediate rails;
• every digital, analog, transceiver, processor, memory and I/O rail;
• DC tolerance, ripple, transient step, remote-sense and decoupling target;
• power-up, power-down, uncontrolled-input-loss and reset requirements;
• ambient, airflow, board area, qualification and production lifetime.

TIDA-050000: hardware-configurable power for 7-series devices #

TIDA-050000 is a practical 5 V, 6 A prototyping reference with thirteen hardware-configurable outputs: eight bucks, four LDOs and an optional DDR termination function. It defines three assembly variants rather than one universal build.

Variant 006 targets Artix-7. The published rail table assigns the high-current VCCINT/VCCBRAM path to TPS568215, DDR power to TPS62067, and lower-current auxiliary, ADC, transceiver and I/O jobs to TPS65023B outputs. Variant 007 targets Spartan-7 with the same main devices and more unused channels available for I/O or peripherals. Variant 008 targets Zynq-7000 and omits TPS568215 in the lowest-power configuration; TI says TPS56C215 can be assembled when the core requirement rises.

Vendor Reference Design

The hardware-set approach avoids a custom EEPROM or OTP image, but it does not avoid configuration control. Resistor population, TPS65023B default pins, optional devices, rail net names and stuffed variant become part of the released BOM. An Artix-7 board with multi-gigabit transceivers can require VMGTAVCC and VMGTAVTT rails that a basic Spartan-7 build does not use. A Zynq-7000 board adds processing-system, MIO, DDR and reset relationships.

AMD's current Spartan-7 data sheet recommends VCCINT and VCCBRAM first, then VCCAUX, then VCCO, with reverse order for shutdown. For Zynq-7000, the processing system adds a stricter integrity condition: PS_POR_B must remain Low until VCCPINT, VCCPAUX and VCCO_MIO0 reach their minimum operating levels. The current AMD advisory also gives the preferred PS order as VCCPINT, VCCPAUX, then VCCO_MIO0. A regulator power-good chain must therefore control reset and external I/O behavior; nominal converter soft-start delays alone are not a complete sequence.

Zynq UltraScale+: choose among three different TI strategies #

A scalable discrete prototype #

TIDA-01480 is the direct UltraScale+ predecessor to TIDA-050000. Its documented prototype range is ZU2CG through ZU5EV, using the C784 package context described in the guide. The design combines TPS65023 or TPS65023B with TPS568215, TPS56C215, TPS62067, TPS51200 and TPS22920 roles according to the selected cost, performance and power-domain variant.

This route is attractive when a development team wants visible, hardware-configurable rails and a socketed power card. Its limitation is equally useful: TI names the supported device range. A ZU9EG or ZU19EG procurement line cannot inherit the ZU2CG–ZU5EV phase count, current limit or connector rail map without a new PDM calculation and board-level verification.

A programmable multirail PMIC #

TIDA-01393 centers on the TPS65086x family. The default reference assembly uses TPS6508641 and targets a ZU3EG-style full-domain-flexibility map. The PMIC integrates three buck converters, three external-FET buck controllers, LDOs, a DDR termination LDO, load switches, control inputs and power-good outputs. TI also publishes pre-defined TPS650864x variants and the user-programmable TPS65086100 route.

The PMIC can coordinate rails compactly, but the OTP or NVM contents are part of the electrical design. A purchase order for “TPS650861” without the exact orderable code, programmed state, image checksum and programming responsibility is incomplete. External MOSFETs and inductors must also be scaled from the real current; TIDA-01393 explicitly treats CSD87381P as one implementation point rather than an unlimited power stage.

At the July 30, 2026 review, TI lists TPS650861 and TPS650864 as active. That does not make every pre-programmed suffix interchangeable. The factory OTP map, package, reel quantity and temperature grade must match the released configuration.

A current module-based proof of concept #

TIPA-010000, published in April 2026, is the most current TI design in this evidence set. It proposes two compact single-stage power trees around XCZU9EG-2FFVB1156E using minimum rail consolidation. The 12 V path uses TPSM843B22 for the 0.85 V, 19 A digital rail, TPSM8F7420 quad-output modules for VCCO and selected analog jobs, and TPSM82912 modules for smaller rails. The 5 V path uses two paralleled TPSM8287A15M modules for the same 0.85 V load case, TPSM82816 modules for VCCO, and TPSM82813 modules for smaller rails.

The figure is a conceptual redraw of the two official block diagrams. It preserves the stated OPN, core load and device roles while leaving detailed rail consolidation in the HTML tables and current PDM output.

Those area, efficiency and loss figures are TI estimates for the documented April 2026 configuration, based on data-sheet curves and a simplified architecture that delivers less total output power than the ZCU102 evaluation board. They must not be quoted as measured performance for another OPN, workload, switching frequency or thermal environment. At this review, TI lists TPSM843B22, TPSM8F7420APG, TPSM8287A15M, TPSM82816 and TPSM82813 as active products.

High-current Virtex UltraScale+ and Versal paths #

TIDA-050020 addresses one difficult job: a high-current Virtex UltraScale+ VCCINT rail. TI describes a 0.85 V, 200 A-class six-phase design using TPS53681 and CSD95490Q5MC smart power stages. TPS53681 adds PMBus configuration, NVM, voltage and compensation adjustment, and telemetry for input, output, current, power, temperature and faults. The secondary controller output can support an auxiliary rail.

Hardware Verified

This is not a complete Virtex board power tree. It does not eliminate the need to design VCCAUX, VCCBRAM, transceiver, I/O and configuration rails or to check AMD package-current and PDN limits. Lifecycle is also now material: TI lists TPS53681 as active but CSD95490Q5MC as not recommended for new designs. A substitute smart power stage cannot be approved from current rating alone; PWM logic, current and temperature reporting, fault behavior, package footprint, compensation and thermal interface must all be revalidated.

PMP22165 extends the same managed-power concept to a Versal reference. Its published 2020 test report pairs a user-programmable TPS650861 system-rail board with the TPS53681 multiphase EVM for a main 0.8 V, 165 A rail. TI reports 7.7 mV peak-to-peak ripple at a 138 A static load and transient results within the stated 0.8 V ±3% band under the documented setup. These measurements are useful evidence for that board and configuration, not a performance guarantee for a current Versal OPN.

The report shows a staged startup beginning with bias and 3.3 V, followed by the high-current 0.8 V rail and the remaining main, auxiliary and I/O rails. Current AMD Versal guidance, however, requires the exact PDM power-management scenario and device data sheet to control rail grouping and sequence. UG863 distinguishes minimum-rail and full-power-management scenarios, and POR_B must remain asserted until the required domain supplies are valid. Preserve the PMP22165 sequence as reference evidence, then regenerate the actual order from current PDM for the selected Versal device.

Sequence, telemetry and reset are separate control jobs #

Power-good signals can gate the next rail, but they usually indicate a regulator threshold rather than final pin-level settling. I2C on TPS650861 controls and reads a PMIC; PMBus on TPS53681 adds rich telemetry and fault information. Neither bus replaces an oscilloscope measurement of ripple, droop, overshoot, monotonic ramp and uncontrolled shutdown at the qualified sense point.

Define ownership explicitly:

• which device enables each rail or group;
• which power-good combination advances the sequence;
• which controller asserts and releases PS_POR_B or POR_B;
• where PMIC OTP, controller NVM and sequencer configuration are stored;
• which host captures first-fault telemetry and how it survives input collapse;
• how rails discharge and how back-power through I/O, transceivers or peripherals is prevented.

BOM and lifecycle controls for a TI FPGA power design #

The regulator base number is only the beginning of the production record. A controlled TI power BOM should preserve:

1. The exact FPGA OPN, PDM or XPE file, tool version and approved load assumptions. 2. The named TI reference design, revision and every deliberate deviation. 3. Full orderable power-device codes, packages, temperature grades and packing options. 4. PMIC OTP or user-programmed image, PMBus NVM file, checksums, addresses and programming procedure. 5. External MOSFET or smart-stage code, phase count, inductor, current-sense network and compensation. 6. Sequencer code, threshold, delay, reset truth table and fault response. 7. Remote-sense routing, critical capacitor list, stackup and thermal design. 8. Current lifecycle evidence, PCN/PDN review and an approved redesign path for NRND parts.

Do not treat a newer TI part suggested by a product page as a drop-in replacement. For CSD95490Q5MC, the correct RFQ response is to flag the NRND status and ask engineering to select and validate a current controller-stage combination. For a TPS650861 design, confirm who programs the blank device and how the programmed lot is identified. For the 2026 module route, preserve the exact module package and parallel-current-sharing implementation rather than quoting only the family name.

Practical RFQ checklist #

Send the following in one controlled request:

• complete AMD FPGA or adaptive-SoC OPN and package;
• board revision, input bus range, environment and qualification level;
• PDM or XPE export with clocks, utilization, transceivers, memory and temperature assumptions;
• rail table with voltage, tolerance, current, transient, noise and sequence requirements;
• selected TI reference design and assembly variant;
• full controller, converter, module, power-stage, sequencer and DDR-PMIC orderable codes;
• programmed-image requirement and checksum for every OTP or NVM device;
• approved inductor, capacitor, sense and thermal-interface parts;
• target quantity, production horizon, date-code rule, packaging and traceability documents;
• explicit statement that substitutions require engineering approval.

Before order release, request current stock, lead time and lifecycle from the authorized channel or qualified supplier. Those values are variable; the reference-design publication date is not supply assurance.

Conclusion #

TI's AMD-Xilinx power portfolio is strongest when its references are used as bounded evidence. TIDA-050000 is a configurable 7-series prototype, TIDA-01393 is a programmable Zynq UltraScale+ PMIC path, TIPA-010000 is a current module-based XCZU9EG proof of concept, TIDA-050020 is a high-current core reference, and PMP22165 is a tested but lifecycle-sensitive Versal starting point. None replaces the current AMD power estimate, device sequence rules or production qualification.

For the cross-vendor method, read AMD-Xilinx FPGA Power Delivery: Design Guide. Compare the vendor-specific evidence with ADI Power Solutions for AMD-Xilinx FPGAs and Renesas PMIC Solutions for AMD-Xilinx FPGAs. The Altera side of the series is covered by Altera FPGA Power Delivery: Design Guide, Powering Altera Agilex 3, 5 and 7 FPGAs, and Stratix 10 and Arria 10 Power Design.

For a controlled build, submit the exact FPGA OPN, PDM or XPE file, rail table, reference-design revision, programmed-device requirements and target quantity. That information lets sourcing preserve the design evidence instead of reducing the request to nominal voltages and base part numbers.

Official references #

• TI TIPA-010000 Power Delivery Architecture for AMD UltraScale+ MPSoC
• TI TIPA-010000 Design Guide, April 2026
• TI TIDA-050000 for Artix-7, Spartan-7 and Zynq-7000
• TI TIDA-01480 for Zynq UltraScale+ ZU2CG through ZU5EV
• TI TIDA-01393 Zynq UltraScale+ PMIC Reference Design
• TI TPS650861 Programmable Multirail PMIC
• TI TPS650864 Configurable Multirail PMIC
• TI TIDA-050020 Virtex UltraScale+ 200 A Core Reference
• TI PMP22165 Versal Power Reference Design
• TI CSD95490Q5MC Product and Lifecycle Page
• AMD Power Design Manager
• AMD UltraScale Architecture PCB Design User Guide UG583
• AMD Zynq UltraScale+ DS925 Power Supply Sequencing
• AMD Zynq-7000 PS Power-On and Power-Off Advisory
• AMD Versal Adaptive SoC PCB Design User Guide UG863
• AMD Versal Simplified Power Sequencing XAPP1375