Altera Cyclone 10 and MAX 10 Power Design

One product tier hides three power architectures #

Cyclone 10 GX, Cyclone 10 LP and MAX 10 are often grouped as cost-optimized programmable logic, but they do not share one power recipe. Cyclone 10 GX has transceiver rails and a mandatory three-group sequence. Cyclone 10 LP uses a simpler core, PLL and I/O rail set, with the exact core voltage fixed by the ordering code. MAX 10 adds nonvolatile configuration and offers fundamentally different single-supply and dual-supply device options.

Altera is the current independent company and FPGA brand. Intel remains in older handbooks, board schematics and reference-design titles because those documents were produced during Intel ownership. Keep that historical label with the document revision, but release the purchasing line against the exact Altera ordering part number (OPN).

The closest existing article is Altera FPGA Power Delivery: Design Guide. That guide sets a portfolio-wide workflow across Agilex, Stratix, Arria, Cyclone and MAX. This article is intentionally narrower: it resolves the rail, sequence, POR, board-BOM and sourcing decisions that differ among Cyclone 10 GX, Cyclone 10 LP and MAX 10. Its engineering evidence and buyer conclusion are therefore distinct rather than a restatement of the overview.

Three current Altera board pages show why the full code matters:

The Cyclone 10 LP board also uses 10M08SAU169C8G as its system controller. In the MAX 10 ordering guide, SA means single supply with analog and flash features and remote-system-update support, while DA means the corresponding dual-supply option. That two-letter field changes the power architecture; it is not a minor logistics suffix.

Build a different rail table for each family #

Altera's current power-support page directs Cyclone 10 and MAX 10 designs to the family Early Power Estimator (EPE), then to the Quartus Prime Power Analyzer when an implemented design is available. The estimate must include the exact density, package, I/O standards, transceiver use, clocks, toggle rates, memories, DSP blocks and junction-temperature assumption. A development-board regulator rating is not a substitute for that load case.

Cyclone 10 GX: core, transceiver and I/O groups #

The current Cyclone 10 GX power-management handbook places VCC, VCCP, VCCERAM, VCCR_GXB and VCCT_GXB in Group 1. VCCPT, VCCH_GXB and VCCA_PLL form Group 2. VCCPGM and the selected VCCIO rails form Group 3. VCCBAT is outside those groups and has no sequencing requirement, but it must still be handled according to the security-key use case and pin guide.

This is not a SmartVID architecture. The core supply is set from the exact device requirements and power estimate rather than negotiated through the Agilex or Stratix 10 PMBus flow. The regulator still needs adequate static tolerance, transient response, remote-sense strategy, thermal margin and PDN impedance.

Cyclone 10 LP: the OPN selects the core-voltage class #

Cyclone 10 LP uses VCCINT at either 1.0 V or 1.2 V, and the two voltage classes have different ordering codes. VCCD_PLL follows the selected core voltage and may share its source with VCCINT only with the isolation treatment allowed by the pin guide. VCCA is 2.5 V and must be powered even if a PLL is unused. VCCIO is selected bank by bank from the supported I/O voltages.

The current data sheet requires all supply ramps to be strictly monotonic without plateaus. It also requires all VCCA pins to be powered together and all VCCIO banks to be powered during operation. The Cyclone 10 LP POR circuit waits for VCCINT, VCCA and the VCCIO banks containing configuration and JTAG pins to cross their trip points before releasing nSTATUS. If the board cannot meet the selected fast or standard POR ramp window, the handbook says to hold nCONFIG low until every supply is stable.

MAX 10: choose single supply or dual supply first #

A MAX 10 single-supply device accepts a 3.0 V or 3.3 V external supply at VCC_ONE and VCCA, then uses its internal regulator to create the 1.2 V core level. Separate VCCIO regulators are still required when an I/O bank uses a different voltage. This path reduces external core-regulator count but has lower core and I/O performance than the dual-supply option.

A dual-supply MAX 10 requires external 1.2 V and 2.5 V supplies for core logic and periphery operation. It can use efficient switching converters and adds separate VCCINT, VCCD_PLL, VCCA_ADC and I/O considerations depending on the feature option and package. Do not infer ADC pins, flash access control, remote system update or package migration from the density alone; the SA/SC/SL and DA/DC/DD/DF feature codes define those boundaries.

Sequencing and POR are not interchangeable #

Cyclone 10 GX uses threshold-gated groups #

All Group 1 rails may ramp in any order, but every Group 1 rail must reach at least 90% of nominal before Group 2 begins. Group 2 follows the same rule before Group 3 begins. Every rail must ramp monotonically and the complete event must meet the selected POR timing.

Altera permits Group 3 rails to be combined with Group 2 only when they share the same voltage and regulator as VCCPT, and only when that consolidation does not drive unpowered GPIO or transceiver pins. This is a narrow electrical exception, not permission to merge all rails of the same nominal voltage.

The recommended power-down path reverses the group relationship: bring Group 3 near ground before Group 2, then Group 2 before Group 1, with all rails fully down within 100 ms. For an uncontrolled input collapse, the current guide defines alternative required voltage-differential and residual-voltage conditions. The system BOM may therefore need input-failure detection, controller hold-up, fast regulator disable and discharge paths even if the normal on/off sequence is correct.

Cyclone 10 LP relies on monotonic ramps and POR control #

Cyclone 10 LP does not use the GX three-group table. Its review should instead prove the correct voltage class, simultaneous VCCA behavior, monotonic ramps, configuration-bank VCCIO validity and the selected POR timing. Externally driven I/O must remain within the handbook's hot-socketing limits while the target bank is unpowered.

MAX 10 generally has no mandatory rail order #

The current MAX 10 configuration guide states that there is no required power-up sequence for the monitored voltages. That does not make enable timing irrelevant. Altera's design guideline recommends sequencing a multi-rail system for long-term reliability, and every rail must meet its ramp and recommended-operating limits.

The POR circuit monitors regulated VCC_ONE, VCCA and the configuration-bank VCCIO for single-supply devices, or VCC, VCCA and those VCCIO banks for dual-supply devices. It does not monitor every dual-supply rail. With instant-on enabled, configuration begins with the shortest path after the monitored supplies trip, so a slow unmonitored rail or late external peripheral can become a system-level startup fault even though the FPGA's POR logic behaved as documented.

For bench acceptance, capture cold start, commanded shutdown, abrupt input loss and restart after a latched fault. Probe at the FPGA rail or documented remote-sense point, not only at the regulator output. Archive the waveform scale, input voltage, temperature, load image, configuration mode and board revision.

Use current board evidence without copying it blindly #

Evaluation Board BOM

Cyclone 10 GX: two official board power generations #

The current Cyclone 10 GX development-kit guide preserves two board variants around the same 10CX220YF780E5G FPGA. The production DK-DEV-10CX220-B “Power Solution 2” table uses configured MPS devices including MPM3690GBF-50D-0011 for the 0.9 V rail, MPM3695GRF-25-0037 for 3.3 V, multiple MPM3650CGQW-C879-Z rails, MPM3632SGPQ-C879-Z, MPM3612GLQ-C879-Z, MPM3804GG-C879-Z, TPS51200DRCR for VTT and LTC4365CDDB-1#TRMPBF for input soft-start/protection.

The earlier DK-DEV-10CX220-A “Power Solution 1” uses Enpirion devices such as EM2130L, EM2130H, EN6337, EN6347, ER3110, ER3105, ER2120, EP5348, EY1501, EV1320 and ES1010. These are revision-specific board BOMs. They demonstrate complete rails and control, but they are not two interchangeable approved-alternate lists. The configured MPS suffixes and the older Enpirion implementation must remain attached to their board schematics, programming data, compensation and lifecycle review.

Cyclone 10 LP: compact integrated regulators #

The Altera Cyclone 10 LP evaluation board uses 10CL025YU256I7G and documents EN5329QI as a 2 A integrated-inductor buck, EN5339QI as a 3 A integrated-inductor buck and two EP5358HUI 600 mA converters. Its schematic implements 1.2 V core and PLL-digital rails, a filtered 2.5 V PLL-analog rail, 3.3 V and 1.8 V I/O rails, and current-measurement points.

That board proves one useful 25K-LE, U256 implementation. A 1.0 V Cyclone 10 LP OPN, another package, different I/O-bank plan or heavier logic activity requires a new EPE, regulator and PDN review.

MAX 10: development-board modules and a PMIC reference #

The current MAX 10 development-kit page names 10M50DAF484I6G, while the board guide documents EN2342QI, EN6337QI and EP5358xUI regulators around the dual-supply device and its peripherals. Treat this as evaluation-board evidence for that board revision.

Hardware Verified

TI's TIDA-00607 is the more integrated official reference for a dual-supply MAX 10. It uses TPS65218D0 to provide the FPGA and memory rails, supervisor functions, programmable sequence and peripheral load switches from a 5 V source or single-cell Li-ion input. TI states that the design was tested for industrial operation from –40°C to 105°C. At the July 31, 2026 review, TI marks TPS65218D0 active and lists active full orderable codes including TPS65218D0RSLT. Preserve the package, packing suffix and programmed register/EEPROM image in the purchasing specification.

Monitoring must cover more than power good #

Cyclone 10 GX includes an internal voltage sensor and temperature-sensing diode, and the official development kit adds onboard power measurement, programmable regulators, a power-failure monitor and a discharge circuit. Use those features to debug, but validate ripple and transients with appropriate probes because slow telemetry cannot prove a high-bandwidth rail limit.

The Cyclone 10 LP evaluation kit uses its MAX 10 system controller and ADC path for current measurement and Board Test System reporting. That is a useful pattern for production: a small always-on controller can qualify the input, enable rails, log faults and hold the main FPGA in reset. The controller itself must be powered from a rail that survives long enough to complete controlled shutdown.

MAX 10 POR monitoring covers only the documented configuration-critical supplies. For a dual-supply device, unmonitored VCCINT, VCCD_PLL and VCCA_ADC still need board-level supervision when their failure could corrupt operation or violate an interface. Decide which faults latch, retry or force the system to a safe state, and record the threshold, delay and firmware/configuration revision.

Release the BOM and RFQ as controlled data #

Engineering package #

1. Freeze the complete FPGA OPN, package, speed grade, temperature grade and board revision. 2. Attach the correct Cyclone 10 or MAX 10 EPE file and the implemented-design Power Analyzer report. 3. List every rail, pin group, voltage, tolerance, current, transient target, sequence/POR dependency and allowed sharing rule. 4. Archive the PDN result, schematic, layout constraints, compensation values and probe-point waveforms. 5. For MAX 10, state single-supply or dual-supply explicitly and record instant-on, POR delay and configuration-bank voltages. 6. For Cyclone 10 GX, include the three-group enable logic and uncontrolled-input-loss behavior.

Procurement package #

• Quote full FPGA and regulator orderable codes, including configured suffixes such as -0011, -0037 or -C879-Z where the reference board uses them.
• Record regulator programming files, checksums, resistor options, PMBus or I2C addresses and approved firmware revisions.
• Confirm package, temperature grade, moisture-sensitivity handling, packing method, date-code rule and lot traceability.
• Treat the older Enpirion BOMs as lifecycle-sensitive evidence; do not approve an alternate from nominal voltage and current alone.
• Separate FPGA rails from DDR, Ethernet, clock, USB, fan and connector loads before sizing the input stage.
• Require engineering approval for every rail consolidation, regulator substitution or OPN voltage-option change.

RFQ inputs #

Send the exact FPGA OPN, build quantity, annual usage, input bus, EPE/Power Analyzer output, rail table, qualification requirement and production horizon. If the request copies a development kit, name DK-DEV-10CX220-B, the Cyclone 10 LP evaluation-board revision, DK-DEV-10M50-C or TIDA-00607 explicitly and identify every component already approved for replacement.

Conclusion #

Cyclone 10 GX, Cyclone 10 LP and MAX 10 occupy a similar cost-oriented market position, but their power systems solve different electrical problems. Cyclone 10 GX requires threshold-gated core, transceiver and I/O groups plus fault-aware shutdown. Cyclone 10 LP depends on the correct 1.0 V or 1.2 V OPN, PLL isolation, monotonic ramps and POR timing. MAX 10 begins with a single-supply versus dual-supply choice, then adds monitored-rail, instant-on and external-system sequencing decisions.

For the portfolio method, read Altera FPGA Power Delivery: Design Guide. Stratix 10 and Arria 10 Power Design covers the higher-performance mature-family boundary, while Powering Altera Agilex 3, 5 and 7 FPGAs explains current SmartVID and SDM-based designs. The vendor-specific AMD-Xilinx evidence is separated in ADI Power Solutions for AMD-Xilinx FPGAs, Renesas PMIC Solutions for AMD-Xilinx FPGAs and TI Power Designs for AMD-Xilinx FPGAs, under the common workflow in AMD-Xilinx FPGA Power Delivery: Design Guide.

Before ordering, send the exact OPN, input bus, rail estimate, sequence plan and qualification requirements. Those files let engineering and procurement distinguish a board-specific reference BOM from a production-ready power design.

Official references #

• Altera FPGA Power Solutions Resources
• Altera Early Power Estimators and Power Analyzer
• Altera Cyclone 10 GX Power-Up Sequence Requirements
• Altera Cyclone 10 GX Power-Down Requirements
• Altera AN 692: Power Sequencing Considerations
• Altera Cyclone 10 GX FPGA Development Kit
• Altera Cyclone 10 GX Development-Kit Power Tables
• Altera Cyclone 10 LP External Power-Supply Requirements
• Altera Cyclone 10 LP Recommended Operating Conditions
• Altera Cyclone 10 LP FPGA Development Kit
• Altera Cyclone 10 LP Evaluation-Board Components
• Altera MAX 10 Device Ordering Information
• Altera MAX 10 Power Management User Guide
• Altera MAX 10 POR-Monitored Rails
• Altera MAX 10 Board Power-Up Guidelines
• Altera MAX 10 FPGA Development Kit
• Texas Instruments TIDA-00607 MAX 10 Power Reference Design
• Texas Instruments TIDA-00607 Test Report
• Texas Instruments TPS65218D0 Product and Lifecycle Page
• Altera Independent-Company Announcement