Renesas PMIC Solutions for AMD-Xilinx FPGAs

The official evidence covers two different power architectures #

Renesas has published useful AMD-Xilinx power references, but they do not form one interchangeable PMIC family. The official evidence divides into two architectures and two design generations:

• compact 5 V input reference boards using ISL91211AIK and ISL91211BIK multi-output PMICs for Artix-7, Spartan-7 and Zynq-7000;
• 8 V to 13.2 V demonstration boards using digital power modules and point-of-load regulators for named Zynq UltraScale+ MPSoCs.

That distinction matters to both engineering and procurement. The 7-series boards show how a programmable multi-output PMIC can cover core, auxiliary, memory and I/O jobs with internal rail sequencing. The UltraScale+ boards show a wider-input, higher-current architecture with PMBus control, explicit rail consolidation and separate cost-optimized and power-optimized use cases. Neither path is a universal Renesas recipe for every AMD device.

The closest existing article is AMD-Xilinx FPGA Power Delivery: Design Guide. That overview compares ADI, Renesas, TI and MPS evidence at system level. This article is separate because it answers a narrower decision: which exact Renesas reference architecture applies, what the published rails and device codes mean, and whether the historical BOM can still be released for a new product.

The named family or device range is part of the claim. Do not extend the Artix-7 board to Versal, the small Zynq UltraScale+ use case to a ZU19EG, or the large-device demonstration board to a different input bus without a new rail analysis.

What the ISL91211 PMIC architecture actually provides #

The ISL91211AIK and ISL91211BIK are four-phase programmable PMICs. The AIK version arranges the four phases as a three-output 2+1+1 architecture; the BIK version provides four single-phase outputs. Renesas specifies up to 5 A peak capability per phase, a 2.7 V to 5.5 V supply range, remote voltage sensing, independently programmable output voltage and dynamic voltage scaling, plus overvoltage, undervoltage, overcurrent and overtemperature protection.

The PMIC data sheet also exposes I2C and SPI interfaces, GPIO and multi-purpose I/O resources. Output defaults, startup behavior and interface choices are therefore configuration-controlled design data, not incidental software settings. The released manufacturing package needs the approved register or OTP configuration, bus address, enable logic and fault response together with the physical part number.

Renesas states that the three FPGA reference designs internally manage power-up and shutdown sequencing of their PMIC rails without an external sequencing controller. That reduces the component count for the demonstrated rail set. It does not remove system-level reset and sequence obligations. External converters, I/O banks, DDR devices, clocks and the FPGA power-on-reset pins must still reach valid states in the order required by the selected AMD device.

The PMIC topology also changes the layout problem. A nominal “20 A total” statement is not a rail guarantee. The current available to one output depends on phase assignment, switching conditions, thermal environment and the programmed protection limits. Renesas instructs designers to keep power loops short and wide, route remote-sense VOUT and RTN directly to the load, keep those traces away from switching nodes, and match the phase-path resistance in dual-phase operation. Copying only the schematic symbols without the layout and configuration controls discards a large part of the reference design.

Current lifecycle changes the design decision #

As checked on 28 July 2026, the official Renesas product page marks ISL91211BIK obsolete and not recommended for new designs; the same product page covers the AIK/BIK reference family and lists DA9121 and DA9122 as alternatives. Those alternatives are not presented as drop-in replacements for the AMD-Xilinx reference boards. They use different product architectures and require a new rail map, footprint, configuration and validation review.

The distinction is simple:

• for an installed legacy product, the ISL91211 reference package remains valuable for repair, controlled last-time sourcing and root-cause analysis;
• for a new design, it is architecture evidence, not permission to copy an obsolete BOM;
• for a redesign, an active PMIC or discrete regulator solution must be sized from the current FPGA load case and validated as a new power system.

Do not silently replace ISL91211AIK with the currently active ISL91211A, or ISL91211BIK with ISL91211B. The active devices use a different WLCSP package and the official product page does not claim drop-in compatibility with the 35-ball BGA reference-board parts.

Three 7-series reference boards and their rail roles #

Renesas announced the three ISL91211 reference boards in March 2020 as tested, complete solutions. The company also stated that user guides, schematics, BOMs and PCB layout files were supplied. The value of these boards is their explicit division of the rail jobs.

Artix-7: ISL91211A-BIK-REFZ #

The Artix-7 board combines both ISL91211AIK and ISL91211BIK, an ISL80030 3 A synchronous buck regulator and an ISL21010DFH312 voltage reference. The two PMICs cover the multiple FPGA and memory supply roles, while ISL80030 supports VCCO or VCC_IO choices at 3.3 V, 2.5 V and 1.8 V. ISL21010DFH312 supplies the published 1.25 V XADC reference function.

An orderable FPGA example such as XC7A100T-2FGG484I identifies the Artix-7 family, speed grade, package and industrial temperature context, but it does not prove that the reference board has sufficient current for the intended utilization. Run the current 7-series Xilinx Power Estimator with the real clocks, logic activity, block RAM, DSP, I/O and transceiver assumptions before allocating PMIC phases.

Spartan-7: ISL91211BIK-REF2Z #

The Spartan-7 board uses ISL91211BIK plus ISL80030. Renesas assigns the PMIC to VCCINT, VCCBRAM, VCC_DDR, VCCAUX and VTT roles, while ISL80030 supports the 3.3 V, 2.5 V or 1.8 V VCCO and VCC_IO choices. The reference is attractive where a small device and memory interface fit the four-output PMIC architecture.

A code such as XC7S50-1CSGA324I still needs its own power estimate and bank-voltage plan. VCCO follows the actual I/O standards; VCC_DDR and VTT depend on whether external memory is present and which memory technology is selected. Renesas stated support across DDR3, DDR3L, DDR4, LPDDR2 and LPDDR3 configurations in the reference-design set, but that is not a license to populate every memory option from one unchanged BOM.

Zynq-7000: ISL91211AIK-REFZ #

The Zynq-7000 board uses ISL91211AIK, ISL9123 and two ISL80030 converters. Renesas assigns ISL91211AIK to VCCINT, VCCBRAM, VCC_DDR and VCCAUX, ISL9123 to VTT, and the two ISL80030 devices to VCCO and VCC_IO choices.

Zynq-7000 adds processor-system rails and reset behavior that cannot be inferred from the Artix-7 or Spartan-7 diagrams. For XC7Z020-2CLG400I, for example, procurement must retain the full device code while engineering separately records processor-system core, auxiliary, MIO, DDR, PLL and programmable-logic rail requirements.

AMD's current Zynq-7000 technical reference manual says the processor-system and programmable-logic supplies are independent, but the processor-system supply must be present whenever programmable-logic power is active. It also requires PS_POR_B to remain asserted low until VCCPINT, VCCPAUX and VCCO_MIO0 have reached their minimum operating levels. The AMD design advisory gives a recommended processor-system order of VCCPINT, then VCCPAUX, then VCCO_MIO0 and defines threshold relationships for protecting eFUSE integrity. A PMIC's internal channel order must be checked against those device-level conditions and the board's external rails.

Zynq UltraScale+ uses a different Renesas power model #

Renesas currently lists ISLUSPLUS-UC1DEMO1Z and ISLUSPLUS-UC2DEMO1Z as active demonstration boards. Both provide power-up and power-down sequencing and a PMBus interface, but they address different device sizes and rail-consolidation policies.

UC1: consolidated, always-on and cost-oriented #

UC1 is stated for ZU2CG, ZU2EG(A), ZU3CG and ZU3EG devices. Its user guide specifies an 8 V to 13.2 V input. The published reference combines core and processor-system loads aggressively:

These are demonstration-board output specifications, not guaranteed current requirements for every listed MPSoC. The combined Rail 1 is valid only when the chosen device, operating-voltage option, utilization and system policy allow that consolidation.

UC2: separated high-current rails for larger devices #

UC2 is stated for ZU11EG, ZU15EG, ZU17EG and ZU19EG. Its guide also specifies an 8 V to 13.2 V input, but separates the highest-current functions:

The current numbers document the demonstration-board design point. They must not be copied into an RFQ as the required rating for another Zynq UltraScale+ configuration. Use AMD XPE for the exact device, speed grade, package, voltage option, transceiver population, VCU use, memory and logic workload.

AMD's current Zynq UltraScale+ data sheet states that processor-system and programmable-logic regions are isolated and their supplies can be powered in either broad order. The required sequencing inside each region, voltage tolerances, ramp conditions and rail-consolidation permissions still come from the exact data-sheet revision and design configuration. The UC1 and UC2 PMBus sequence files are therefore evidence for those boards, not generic sequence firmware.

Monitoring, sequencing and configuration ownership #

The 7-series and UltraScale+ paths require different production controls.

For an ISL91211-based legacy design, preserve:

• the exact AIK or BIK device and 35-ball package code;
• the programmed output defaults, phase allocation and dynamic-voltage settings;
• I2C or SPI mode, device address and host ownership;
• enable, reset, watchdog, GPIO and interrupt behavior;
• PMIC fault thresholds and the expected response to UV, OV, OC and OT events;
• the FPGA reset release conditions and external-regulator power-good dependencies.

For UC1 or UC2 digital power, preserve:

• every PMBus address, output-voltage and current-limit setting;
• ramp time, turn-on delay, tracking relationship and power-down order;
• nonvolatile configuration image and checksum;
• telemetry limits for VIN, VOUT, IOUT and temperature;
• fault-log retrieval and the production method used to clear or retain faults;
• the exact rail-consolidation use case and the AMD document revision that approved it.

Monitoring is not the same as sequence authority. A PMBus host may read telemetry while hardware power-good chains determine startup. A board-management controller may command shutdown while the FPGA reset pin protects boot state. The design release should name which device owns each action and what happens if the serial bus is unavailable.

Lifecycle audit: reference validity is not BOM availability #

The official Renesas pages checked on 28 July 2026 show a mixed lifecycle picture:

This is why an active demonstration-board page and an obsolete component page can coexist. The board remains documented and may still be orderable as a development tool, while the semiconductor BOM is no longer recommended for a new production design. At RFQ, check each line item, not only the board status.

Controlled BOM and RFQ checkpoints #

Start the sourcing package with the exact FPGA or MPSoC orderable code. A family-only request such as “Zynq UltraScale+ power” does not define current, voltage option, package, transceiver rails or qualification grade.

An obsolete PMIC found in the independent market may be appropriate for a controlled repair build, but only after authenticity, storage, moisture sensitivity, solderability, date code and traceability checks. It is not a neutral way to avoid redesign. Conversely, a currently active regulator is not automatically an approved replacement if it changes footprint, compensation, PMBus behavior, transient response or thermal performance.

Engineering release checklist #

1. Freeze the full FPGA or MPSoC OPN, package, speed and qualification grade. 2. Run the current AMD XPE with the real clocks, utilization, transceivers, memory and ambient assumptions. 3. Build a rail table covering voltage, tolerance, static and transient current, ripple, sequencing, discharge and monitoring. 4. Select the closest Renesas evidence path: 7-series PMIC board, UC1, UC2 or none. 5. Record where the new design differs from the official board in input bus, FPGA, rail consolidation, phase count and thermal environment. 6. Verify reset and power-on conditions from the current AMD data sheet, including PS_POR_B rules for Zynq-7000. 7. Audit every Renesas device on the official lifecycle page; treat obsolete and NRND lines as redesign gates. 8. Preserve configuration, checksum, PMBus or I2C address and fault policy as controlled BOM data. 9. Validate startup, shutdown, brownout, transient, ripple, PDN and thermal behavior on the production-layout prototype. 10. Release alternates only after the same simulations and hardware tests, then communicate the approved suffixes to procurement.

Conclusion #

Renesas provides two strong kinds of AMD-Xilinx power evidence. The ISL91211 boards show a compact, internally sequenced PMIC architecture for Artix-7, Spartan-7 and Zynq-7000. UC1 and UC2 show how Zynq UltraScale+ designs move toward wider input range, PMBus-managed modules, explicit rail consolidation and higher core current.

The main sourcing conclusion in 2026 is equally clear: much of the named reference BOM is now legacy. Engineers can reuse the rail logic, evidence and test methods, but a new product must pass a line-by-line lifecycle and redesign review. Buyers should never convert “official reference design” into “currently approved production BOM” without that gate.

For the system-level workflow, read AMD-Xilinx FPGA Power Delivery: Design Guide. To compare a broader currently documented vendor library, see ADI Power Solutions for AMD-Xilinx FPGAs. The independent-vendor counterpart is Altera FPGA Power Delivery: Design Guide, and Powering Altera Agilex 3, 5 and 7 FPGAs shows how current FPGA order-code power options change the regulator decision.

For a Renesas-based FPGA power RFQ, send the exact FPGA OPN, XPE output, input bus, reference-board revision, controlled power configuration and target quantity. LimChip can then check the component and lifecycle record while substitution approval remains with the engineering owner.

Official references #

• Renesas PMIC Reference Designs for Xilinx FPGAs and SoCs
• Renesas ISL91211AIK and ISL91211BIK Data Sheet
• Renesas ISL91211BIK Product and Lifecycle Page
• Renesas ISL91211B Active Product Page
• Renesas ISLUSPLUS-UC1DEMO1Z Zynq UltraScale+ Reference Board
• Renesas ISLUSPLUS-UC1DEMO1Z User Guide
• Renesas ISLUSPLUS-UC2DEMO1Z Zynq UltraScale+ Reference Board
• Renesas ISLUSPLUS-UC2DEMO1Z User Guide
• Renesas Product Supply Policy and Lifecycle Definitions
• Renesas ZL9010M Digital Power Module
• Renesas ZL9006M Digital Power Module
• Renesas ISL8271M Digital Power Module
• Renesas ISL8277M Digital Power Module
• Renesas ISL85003 Synchronous Buck Regulator
• Renesas ISL85415 Synchronous Buck Regulator
• AMD Zynq-7000 SoC Technical Reference Manual: Power Pins
• AMD Zynq-7000 SoC Technical Reference Manual: External Reset Signal Pins
• AMD Zynq-7000 Power-On and Power-Off Design Advisory
• AMD Zynq UltraScale+ MPSoC Data Sheet: PS-PL Power Sequencing
• AMD Xilinx Power Estimator