MPS Power Solutions for AMD-Xilinx FPGAs

Choose the MPS path from the FPGA and evidence #

Monolithic Power Systems offers several genuinely different ways to power an AMD-Xilinx FPGA: a compact multi-output PMIC, integrated-inductor modules, scalable digital converters, low-noise RF data-converter rails and an automotive-qualified wide-input tree. They are not interchangeable product lists. Each route is tied to a particular FPGA family, input bus, rail-consolidation decision, current range and evidence level.

The closest existing article is AMD-Xilinx FPGA Power Delivery: Design Guide. That overview compares ADI, Renesas, TI and MPS at system level. This article is intentionally narrower: it resolves which published MPS design applies, which exact configured power-device codes belong in the BOM, who owns sequencing and telemetry, and which historical reference parts now require a lifecycle gate. Its search intent and release decision are therefore different from the cross-vendor overview.

Start with the full AMD ordering code, not a family label. XCZU3EG, XCZU19EG, XCZU39DR and XCZU49DR indicate different processing, programmable-logic, transceiver and RF-converter loads even before package, speed and temperature suffixes are added. AMD's current Power Design Manager 2026.1 release supports the complete UltraScale+ portfolio and is the preferred estimator for new UltraScale+ work. The released estimate must reflect the implemented clocks, utilization, hard IP, memory, transceivers, workload and thermal assumptions.

The current MPS AMD reference-design portal also lists Virtex, Kintex, Versal, Artix and Spartan families. Treat that coverage page as a route to design assistance, not proof that one public schematic has been tested for every device named on the portal. AMD itself distinguishes hardware-verified references from non-hardware-verified vendor solutions and says availability remains the vendor's responsibility.

Compact PMIC designs preserve programmed identity #

Spartan-7 uses a configured MP5470 path #

MPS publishes a cost-optimized Spartan-7 reference using MP5470-0014 and MP20075. The MP5470 integrates four buck converters with I2C and multiple-time-programmable settings; MP20075 provides the DDR termination function where the memory design requires it. The suffix -0014 is not decorative. It identifies the programmed option used by the design.

That reference is a useful starting point for exact Spartan-7 devices such as an XC7S family OPN, but it does not define the current for a new board. Xilinx Power Estimator remains the AMD estimator for pre-UltraScale+ families. Confirm VCCINT, VCCAUX, VCCO, memory and any transceiver-related rails against the selected device, I/O standards and utilization before reusing the PMIC configuration.

XCZU3EG uses two different MP5475 configurations #

The MPS XCZU3EG PMIC design uses one MP5475-001B, one MP5475-001C and two MP2002A LDOs. MPS publishes different internal orders for the two PMICs:

• MP5475-001B: Buck A, then Buck C, then Buck B, then Buck D;
• MP5475-001C: Buck A, then Buck B, then Bucks C and D.

The current generic MP5475 product page marks the device Active and describes configurable MTP sequencing, I2C control and telemetry. That status does not by itself guarantee immediate availability of the historical -001B and -001C programmed variants. Procurement must request the exact code or obtain MPS-approved programming data and a controlled configuration process. A quote for “MP5475” is incomplete.

The PMIC can report and control useful power data, but board-level ownership remains broader than the chip. The design still needs a controller policy for enable dependencies, fault latching, reset release, logging and safe shutdown. A PMBus or I2C register map is telemetry capability, not a completed system fault strategy.

Scalable modules cover high-current and dense rail sets #

MPS's 6 V to 16 V Zynq UltraScale+ MPSoC reference page lists XCZU2CG, XCZU3CG, XCZU4CG, XCZU5CG, XCZU6CG, XCZU7CG, XCZU9CG, XCZU2EG through XCZU19EG, and XCZU4EV/5EV/7EV. Its published BOM combines eight MPM3606A modules, two MPM3610A, two MPM3630, two MPM3620A, one MPM3695-25-0022, two MPM3695-10-0022 and one MP20075.

This is a scalable family design, not a claim that every listed device consumes the reference maximum. The number of high-current phases, output capacitance, compensation, copper area and thermal solution must follow the PDM result for the selected package and workload. EV devices add the video-codec rail; EG and CG devices do not have identical rail needs. Memory choice changes the VCCO_PSDDR and termination job, while enabled GTR or PL transceivers add separate analog domains.

The configured module codes matter twice. First, the -0022 option can carry voltage, PMBus and start-up behavior expected by the reference. Second, lifecycle can invalidate a copied BOM. As checked on August 1, 2026, the current MPS high-current module table marks MPM3695-25 not recommended for new designs, while MPM3695-10 remains Active. The smaller current MPM3695-20 is Active, but it must not be presented as an automatic drop-in replacement for MPM3695-25. Package, current definitions, control, telemetry, compensation, thermal behavior and board layout require a fresh MPS/AMD review.

RFSoC separates digital rails from converter noise #

An RFSoC power system has two different signal-integrity problems. The programmable logic and processor domains need high-current, fast-transient rails. The integrated ADC and DAC domains need low-noise supplies whose filtering and operating mode are validated at the converter, not only at the regulator pins.

MPS's current RFSoC Gen 2/3 discrete-reference page names XCZU39DR, XCZU43DR, XCZU46DR, XCZU47DR, XCZU48DR and XCZU49DR. The 12 V architecture lists MP8796B-3333, MP8796B-0022, MP2332C, MP2326, MP2002A, MP8770C, two MPM3695-10 modules, three MPM3833C modules, three MP20075 DDR regulators and an optional MPQ7962-0010 monitor. MPS reports about 90% total system efficiency and roughly 3.7 square inches including input and output capacitors for that specific published design. Those are board-level design-page figures, not guaranteed results for another RFSoC OPN, stack-up or airflow.

There is an important lifecycle boundary: the current MP8796B product page marks the digital 30 A converter NRFND. The reference remains valuable for rail mapping, PMBus ownership and measured architecture, but a new production release needs an approved redesign path. The Active analog MP8796 is not a PMBus-equivalent substitute; removing the digital interface changes configuration, telemetry and fault management.

For RF converter rails, MPS documents EVREF0102A for the ZCU1275 characterization kit. The board uses MPM3833C and MPM3683-7 modules with post filters. MPS reports that the two sensitive ADC/DAC rails use CLC filtering, with capacitive filters on the remaining converter rails, and that measurements were taken on the ZCU1275 platform. The current EVREF0102A page describes five switch-mode modules and integrated OCP, OVP and UVP. This evidence supports the named board approach; it does not justify copying its filter into a different RFSoC layout without impedance, ripple and spur measurements at the load.

AMD's current DS926 RFSoC sequencing table also varies by generation. ZU2xDR and ZU39DR converter analog rails have no power-up ordering requirement, while ZU4xDR and ZU6xDR require ADC_AVCCAUX before ADC_AVCC, with the reverse order on shutdown. The exact OPN therefore changes the sequencer truth table even within “RFSoC.”

Automotive ZU+ is a bounded wide-input reference #

MPS's automotive Zynq UltraScale+ design is one of the strongest public MPS examples because the reference document includes schematics, BOM, rail distribution, transient plots, thermal data, sequencing waveforms and EMC measurements. It targets ZU2CG through ZU5EG and uses a 4 V to 36 V system range on the published board.

The design also lists MPQ4433 for auxiliary conversion. MPS tested the board at the stated loads and conditions, including a 12 A VCCINT thermal case at 12 V input and 25°C ambient after a two-hour run. The EMC plots are tied to the documented switching frequencies, spread-spectrum setting and load. Keep those conditions next to any engineering claim; do not generalize them to every automotive enclosure or cable harness.

The most important sequencing note is easy to miss: the reference table says power-on sequencing: yes and power-off sequencing: no, needs an external sequencer. Shutting the board down only by removing VIN is a test behavior, not a controlled reverse sequence for a vehicle ECU. A production architecture needs an explicit shutdown owner, stored-fault policy and rail-discharge plan.

The reference specifies MPQ8886-0000-AEC1 and programming through MPS Virtual Bench Pro plus the EVKT-USBI2C-02 interface. Because the public current product search clearly establishes the related MP8886 as Active but does not independently establish availability of that exact automotive programmed code, an RFQ must ask MPS or an authorized source to confirm the full suffix, AEC-Q100 grade, wettable-flank/package option if applicable, MTP image and programming traceability. The other named parts must be checked the same way; several base families remain Active, but the production line is the exact orderable code.

Sequence, monitor and reset as one control system #

AMD's current DS925 revision 1.30, released July 9, 2026, says the Zynq UltraScale+ processor-system and programmable-logic regions are isolated and can be powered independently, but each region still has its own required or recommended sequence. The current UG583 revision 1.29 explains that a minimum five-regulator consolidation can suit many always-on use cases, while full domain power management can require at least nine separately controlled regulators or equivalent regulator/load-switch functions. That choice changes the MPS channel count and control graph before any part is ordered.

For every rail, the schematic and firmware release should identify:

• the source converter and exact configuration code;
• enable dependency, ramp target, power-good threshold and allowed timeout;
• voltage/current/temperature telemetry source and polling rate;
• fault response, retry count, discharge path and shutdown order;
• reset or POR signal released only after the required domains are valid;
• laboratory measurement points for ripple, transient and sequence validation.

PMBus telemetry is especially useful on high-current MPM3695 or MP8796B-style paths, but it must be matched to the supervisory controller. If an older digital regulator is redesigned around an analog or different digital part, the register map, scaling, alert behavior, nonvolatile configuration and production-programming flow can all change. Firmware, test limits and purchasing specifications must move together.

Lifecycle and RFQ controls prevent false equivalents #

As of August 1, 2026, the MPS pages reviewed for this article show a mixed lifecycle picture. MP5475, MPM3695-10, MPM3833C, MP20075, MPQ2166A-AEC1 and MPQ20073-AEC1 are Active. MPM3695-25 and MP8796B are NRFND. Lifecycle labels can change, and an Active base product does not guarantee every OTP/MTP configuration suffix is orderable. Record the page check date and obtain written confirmation for the released code.

Do not approve an alternate only because nominal voltage, current and package appear similar. For a configured PMIC or digital module, the alternate also has to preserve sequence, soft-start, protection thresholds, compensation, telemetry, fault behavior and programming ownership. For RF rails, it must preserve the filter and noise result at the device. For automotive, it must preserve qualification, thermal, EMC and shutdown evidence.

Conclusion #

MPS has credible AMD-Xilinx paths from Spartan-7 and compact XCZU3EG PMICs through scalable Zynq UltraScale+ modules, RFSoC digital and low-noise rails, and a documented automotive ZU+ tree. The value is the range of architectures, not one universal regulator family.

The release rule is simple: bind the exact AMD OPN and current PDM/XPE file to one documented MPS architecture, preserve every programmed suffix, implement both power-up and power-off ownership, and close the lifecycle gate before the purchase order. Historical reference designs remain excellent engineering evidence, but an NRFND controller or module turns a copy-and-buy exercise into a redesign.

For a controlled review, send the exact AMD-Xilinx OPN, PDM or XPE file, input bus, required qualification grade, target quantity and the MPS reference you intend to follow. That package lets engineering and procurement verify the same rail map before stock is committed.

Official references #

• AMD Power Design Manager 2026.1
• AMD Power Efficiency and Hardware-Verified Power-Solution Policy
• AMD Zynq UltraScale+ MPSoC DS925 PS-PL Power Sequencing
• AMD UltraScale Architecture PCB Design Guide UG583: Rail Consolidation
• AMD Zynq UltraScale+ RFSoC DS926 PL Power Sequencing
• MPS AMD Reference-Design Portal
• MPS FPGA Power Solutions
• MPS Spartan-7 Cost-Optimized Reference Design
• MPS XCZU3EG PMIC Power Solution
• MPS Zynq UltraScale+ 6 V to 16 V Module Reference Design
• MPS RFSoC Gen 2/3 12 V Reference Design
• MPS Zynq UltraScale+ RFSoC Compact and Low-Noise Module Article
• MPS EVREF0102A RFSoC Analog Power Module
• MPS Scalable Automotive Power Supply for AMD-Xilinx ZU+
• MPS Automotive ZU+ Full Reference-Design PDF
• MPS MPM3695 High-Current Module Lifecycle Table
• MPS MP8796B Product and Lifecycle Page
• MPS MP5475 Product Page
• MPS MPM3833C Product Page
• MPS MP20075 DDR Termination Regulator
• MPS MPQ2166A-AEC1 Product Page
• MPS MPQ20073-AEC1 Product Page