Stratix 10 and Arria 10 Power Design

Two mature families, two different control planes #

Stratix 10 and Arria 10 remain relevant in installed communications, test, acceleration and industrial platforms, but a power tree cannot be copied from one family to the other. Both devices use multiple voltage domains and both can use SmartVID, yet the control interface, power-option encoding, rail groups and board evidence are different.

Altera is the current independent company and FPGA brand. Intel appears throughout the original Stratix 10 and Arria 10 handbooks, development-kit files and power-vendor reference designs because those documents were published during Intel ownership. Treat that naming as historical document context; use the current Altera device documentation and preserve the original ordering part number (OPN), board revision and regulator configuration.

The closest existing article is Altera FPGA Power Delivery: Design Guide. That guide spans Agilex, Stratix, Arria, Cyclone and MAX. This article is intentionally narrower: it explains the engineering and purchasing decisions that change specifically between Stratix 10 and Arria 10, including the PMBus-based Stratix 10 path, the parallel-VID Arria 10 path, device-specific sequence groups and evidence-backed power-device BOMs.

Start with the full OPN. The Altera Stratix 10 GX transceiver signal-integrity kit is documented with 1SG280LU2F50E2VG or 1SG280HU2F50E2VG. The final V denotes the standard-power SmartVID option. The current Arria 10 GX development-kit page names 10AX115S2F45I1SG. Its power implementation must be resolved from the Arria 10 ordering information, device handbook and board files rather than by applying the Stratix 10 suffix rule.

Stratix 10: SmartVID is part of configuration #

Current Altera Stratix 10 documentation separates standard-power SmartVID devices from fixed-voltage low-static-power devices. A standard-power –V device requires a PMBus regulator dedicated to that FPGA for the VCC/VCCP core supplies. The requirement is architectural: the Secure Device Manager (SDM) reads the device-specific fused VID value and communicates the required voltage to the regulator early in configuration.

The current Stratix 10 power-management guide states that the fused VID lies from 0.80 V to 0.94 V in 10 mV steps. It also distinguishes PMBus master and slave modes and their supported output-data formats. Those details must match the Quartus Power Management and VID settings, physical PMBus address, regulator coefficients and level translation. “PMBus capable” by itself is not proof of compatibility.

Altera's SmartVID resource maintains two evidence levels. A fully validated regulator is regression tested for every Quartus Prime Pro release; an API-validated device is known to be compatible with the SDM power-management API but is not stated to have been physically tested. At the July 29, 2026 article review, Altera lists LTM4677 as the fully validated Stratix 10 regulator. Recheck that live table and the applicable Quartus release before a new design is frozen.

For a fixed-voltage Stratix 10 OPN, do not leave an active SmartVID control path by habit. Use the nominal voltage and tolerance from the exact current data sheet and package guidance. Fixed voltage simplifies the regulator interface, but it does not remove the need for remote sensing, PDN analysis, sequence control, transient testing or rail monitoring.

Arria 10: SmartVID uses parallel logic #

Arria 10 implements SmartVID differently. Its current power-management handbook describes a 7-bit fused VID value representing 0.85 V to 0.90 V. The external regulator output range, including tolerance, is specified as 0.82 V to 0.93 V, with a nominal power-up voltage of 0.90 V and 10 mV steps.

The documented parallel solution uses seven VID pins plus VID_EN. The I/O bank that hosts those signals must already be powered before VID_EN is asserted. Altera recommends a level shifter to isolate the FPGA VID signals from the regulator controller because some codes could otherwise command a voltage above the permitted VCC/VCCP range. VID_EN also needs the documented pull-down and pin assignment.

This is not the Stratix 10 SDM-to-PMBus flow. A purchasing line that substitutes a PMBus controller because it worked on a Stratix board can fail even when its voltage and current ratings appear adequate. The Arria 10 reference circuit must expose the required parallel input behavior, startup voltage and safe isolation, or implement a verified system-controller translation path.

The diagram is a LimChip conceptual redraw from the current Altera power-management guides. It compares interface ownership, not pin-level schematic detail. The exact OPN, Quartus version and regulator data sheet remain controlling.

Rail domains and current sizing #

Both families split the device into core, transceiver, PLL, I/O, configuration and optional processor domains. A regulator count should come from the exact pin-connection guide, not from the number of rows in an evaluation-board power monitor.

For Stratix 10 GX/SX, common domains include VCC/VCCP, VCCERAM, transceiver receiver and transmitter rails, VCCPT, VCCA_PLL, SDM rails and I/O-bank rails. MX, TX and DX devices add family- or tile-specific domains, so a GX power tree must not be generalized to HBM, E-Tile or P-Tile devices.

Arria 10 uses VCC/VCCP, VCCERAM, VCCR_GXB, VCCT_GXB, VCCH_GXB, VCCPT, VCCA_PLL, configuration and I/O rails. SX devices add HPS-related core, PLL and I/O-reference supplies. Each I/O bank has its own VCCIO selection, so the memory and interface plan can change both rail voltage and load.

Current is implementation-dependent. Generate the Early Power Estimator or current supported power-estimation output using the real density, clocks, logic utilization, DSP and RAM activity, transceiver count, I/O standards, HPS load and junction-temperature target. As the design matures, preserve the Quartus Power Analyzer report with the board release.

Sequence by thresholds, not nominal delays #

Arria 10 has three documented power groups. Group 1 includes core, ERAM, transceiver receiver/transmitter and applicable HPS core rails. Group 2 includes VCCPT, high-voltage transceiver, PLL and HPS reference rails. Group 3 contains configuration and I/O rails. Every rail in the earlier group must reach at least 90% of nominal before the next group begins; rails within one group may ramp in any order and every rail must ramp monotonically.

Arria 10 allows some Group 3 rails to be combined with Group 2 when they share the same voltage and regulator as VCCPT, provided the board does not drive unpowered GPIO or transceiver pins. That is a conditional consolidation rule, not permission to merge all 1.8 V rails.

Stratix 10 also uses threshold-gated groups, but the membership changes across GX/SX, MX, TX and DX. Most variants progress through Groups 1, 2 and 3; certain 1SG040 and 1SX040 devices add a Group 4 relationship. E-Tile devices retain additional ordering constraints, including the documented requirement that VCCCLK_GXE be powered before VCCIO_SDM. For configuration via protocol, the current guide requires total rail ramp time below 10 ms and a fast POR selection so PCIe initialization retains enough time.

The figure intentionally keeps family-specific rail lists in the article table rather than shrinking them into an unreadable image. Its single message is that both devices advance only after the previous group crosses the stated threshold, while Stratix 10 may add device- and tile-specific conditions.

Power-down is not an afterthought. The Stratix 10 guide recommends shutting later groups down before earlier groups, bringing all rails fully down within 100 ms, and maintaining documented cross-group voltage differences. It also defines a required collapse behavior when the recommended sequence cannot be followed. The board therefore needs an uncontrolled-input-loss plan: loss-of-power detection, sufficient controller hold-up, rapid disable, discharge where allowed and prevention of alternate back-power paths.

Capture at least cold startup, commanded shutdown, abrupt input removal and restart after a latched fault. Measure at FPGA pins or qualified sense points. The release record should show thresholds, monotonicity, total ramp time, power-good and reset timing, external I/O state and the worst-case voltage difference during collapse.

Evidence-backed BOM starting points #

Reference designs are valuable only when their scope remains attached. They show that a named architecture was built or recommended for a named platform; they do not prove that the same phase count or complete BOM fits every density, package or workload.

Stratix 10 GX module and multiphase paths #

The Altera Stratix 10 GX signal-integrity development board documents LTM4677 plus three LTM4650 modules on the VCC rail, LTM4620 devices on ERAM and transceiver rails, and LTM2987 for power monitoring. ADI's current circuit note presents the LTM4677/LTM4650 path and an updated alternative using two LTM4700 digital-power modules for the core. That alternative is a vendor recommendation tied to the reference context, not a footprint-compatible swap.

Vendor Reference Design

TI's PMP20176 is a separate four-phase, 140 A Stratix 10 GX core reference centered on TPS53647 and four CSD95472Q5MC smart power stages, with a stated focus on the SG2800-I1V variant. The published design uses a 12 V-class input and PMBus for configuration and telemetry. As of July 29, 2026, TI marks both TPS53647 and CSD95472Q5MC active. The original reference still requires a fresh PDN, thermal and transient review for the new board.

Arria 10 module and smart-stage paths #

ADI's Arria 10 FPGA development-kit circuit uses LTC3877 plus LTC3874 for a 105 A-class VCC core implementation, LTM4637 for a 20 A transceiver rail and LTC2977 for eight-channel sequencing, monitoring, margining and fault management. The architecture uses the Arria 10 parallel VID relationship. At this article review, ADI marks LTC3877, LTM4637 and LTC2977 recommended for new designs; every full model suffix and the LTC3874 status still need confirmation at BOM release.

Hardware Verified

TI's TIDA-01419 is a four-phase 150 A Arria 10 GX core reference focused on 10AX115U145IVG, using TPS53647 with CSD95472Q5MC stages. TI publishes steady-state, transient, thermal, startup, shutdown and protection results under the report's stated conditions. Those results apply to that test board and load case; they are not a 150 A requirement for every Arria 10 device.

Monitoring, configuration and fault ownership #

A digitally managed regulator can measure voltage, current and temperature, but the design still needs a declared owner for every state transition. Document which device enables each group, which signal releases FPGA reset, what captures first-fault data and which controller can still act after the input begins collapsing.

For Stratix 10 SmartVID, archive the Quartus constraints, PMBus address, master/slave selection, VOUT format, coefficients, NVM image, checksum and programming procedure. For Arria 10 parallel VID, archive the seven-bit mapping, VID_EN timing, level-shifter part, pull-down, I/O-bank supply dependency and the safe initial voltage.

Telemetry is not a substitute for measurement. Remote-sense and PMBus readings are low-bandwidth control observations; ripple and transient compliance must be probed at the intended device sense point with appropriate bandwidth and grounding. Correlate the oscilloscope record with controller logs and FPGA temperature data.

BOM and RFQ release checklist #

Engineering release #

1. Freeze the complete Stratix 10 or Arria 10 OPN, package, board revision and configuration mode. 2. Attach the current power estimate, assumptions and Quartus Power Analyzer report. 3. Build a rail table with nominal voltage, tolerance, current, transient, noise, sequence group, discharge and monitoring requirements. 4. Identify SmartVID or fixed-voltage behavior from the exact device documentation. 5. Preserve the PMBus or parallel-VID implementation, controller configuration and checksum as controlled design files. 6. Simulate the PDN and verify load step, phase balance, remote sense, thermals and worst-case input. 7. Capture controlled and uncontrolled power waveforms, including I/O back-power checks. 8. Approve alternates rail by rail after schematic, layout, firmware and hardware validation.

Procurement and RFQ release #

• Quote the full FPGA OPN and every controller, power-stage, module, sequencer, supervisor and level-shifter ordering code.
• Preserve programmed, EEPROM, NVM or OTP options; a generic base number is not an acceptable purchase line.
• State package, temperature grade, qualification, terminal finish, packing method, moisture sensitivity and date-code rule.
• Ask for current lifecycle, PCN/PDN history, lot traceability and manufacturer labels before order release.
• Identify the source board or reference design and clearly list every deviation.
• Include target build quantity, annual volume, production horizon and allowed substitutions.
• Keep inductors, current-sense elements and critical capacitors inside the electrical approval boundary; they set loop, transient and thermal behavior.

Conclusion #

Stratix 10 and Arria 10 power design is not one legacy Altera recipe. Stratix 10 standard-power devices place the SDM, PMBus regulator and Quartus configuration in one controlled SmartVID chain. Arria 10 uses a separate parallel-VID implementation with its own startup, I/O-bank and isolation rules. Both families then require device-specific rail groups, threshold-based sequencing, fault-aware shutdown and a traceable production BOM.

For the portfolio-wide method, read Altera FPGA Power Delivery: Design Guide. Powering Altera Agilex 3, 5 and 7 FPGAs shows how the current Agilex generations change the OPN and sequencing decision. The cross-vendor framework is covered in AMD-Xilinx FPGA Power Delivery: Design Guide, with focused vendor evidence in ADI Power Solutions for AMD-Xilinx FPGAs and Renesas PMIC Solutions for AMD-Xilinx FPGAs.

For a controlled power BOM, send the complete FPGA OPN, power estimate, input bus, rail table, configuration files and target quantity. Those inputs allow sourcing to preserve the engineering evidence rather than reducing the request to a list of nominal voltages.

Official references #

• Altera Stratix 10 Power Management User Guide
• Altera Stratix 10 SmartVID Feature Implementation
• Altera Stratix 10 Power-Up Sequence Requirements
• Altera Stratix 10 Power-Down Requirements
• Altera Stratix 10 GX Transceiver Signal Integrity Kit Power Supply
• Altera FPGA SmartVID and Validated Regulator List
• Altera Arria 10 SmartVID Feature Implementation
• Altera Arria 10 Power-Up Sequence Requirements
• Altera Arria 10 GX FPGA Development Kit
• Analog Devices Stratix 10 GX Signal Integrity Kit Power Solutions
• Analog Devices Arria 10 FPGA Development Kit Power Solutions
• Texas Instruments PMP20176 Stratix 10 GX 140 A Reference Design
• Texas Instruments TIDA-01419 Arria 10 GX 150 A Reference Design
• Texas Instruments TPS53647 Product Page
• Texas Instruments CSD95472Q5MC Product Page
• Analog Devices LTM4677 Product Page
• Analog Devices LTM4700 Product Page
• Analog Devices LTC3877 Product Page
• Analog Devices LTC2977 Product Page