ADI Power Solutions for AMD-Xilinx FPGAs

Start with the FPGA load case, not an ADI family name #

Analog Devices offers an unusually broad set of published power trees for AMD-Xilinx programmable logic: compact Spartan-7 concepts, Artix UltraScale+ minimum-rail designs, Zynq-7000 and Zynq UltraScale+ boards, high-current Kintex and Virtex platforms, and managed Versal solutions. That breadth is useful only when the evidence remains attached to the exact FPGA, rail plan and board conditions.

An ADI regulator is not automatically suitable because it appears on another Xilinx board. Freeze these inputs before selecting a power tree:

• complete FPGA or adaptive-SoC ordering code, package, speed and temperature grade;
• AMD power-estimation file for the intended clocks, utilization, transceivers and workload;
• input bus, rail voltages, tolerance, transient current and noise limits;
• permitted rail consolidation and the required power-on and power-off behavior;
• DDR type, I/O-bank voltages, GT resources, peripherals and board-level loads;
• ambient temperature, airflow, PCB copper and qualification requirements.

For example, XC7S50-1CSGA324I, XCAU25P devices, a ZCU104-class ZU7EV, ZU17-2/ZU19-2, XCVC1902 and Versal Prime Gen 2 2VM3858 are not interchangeable “FPGA loads.” They represent different rail counts, current density, processor and transceiver content, sequencing rules and monitoring needs. The official ADI AMD-Xilinx solution library is therefore a navigation system, not a universal approved-parts list.

Read the evidence label before copying the BOM #

The table below classifies the official ADI pages cited in this article. It does not upgrade ADI's stated evidence. A tested board is stronger proof than a proposed rail map, but even a tested board covers only its documented device, configuration and conditions.

Procurement should preserve this evidence level in the approved-vendor-list record. “Used in an ADI FPGA power design” is too vague: the release package should name the source design, document revision or access date, FPGA target, selected topology and validation still required.

Compact 7-series and Artix UltraScale+ solutions #

Spartan-7: a two-device concept, not a tested universal board #

ADI's current Spartan-7 circuit note is explicitly non-hardware-verified. It maps MAX77542AAWU+T to VCCINT, VCCBRAM, VCC_DDR and VCC_IO, with ADP125ACPZ-R7 for VCCADC_AUX. The integration is attractive for a compact device such as XC7S50-class logic, but the page does not prove one MAX77542 configuration for every Spartan-7 package, I/O-bank plan or memory load.

The buyer must obtain the programmed or pin-strapped rail configuration, confirm the WLP/package assembly capability, and keep ADP125 voltage option and packing suffix intact. Engineering must then compare each channel's current, transient and start-up behavior with the exact AMD estimate and data sheet.

Zynq-7000: strong board evidence with a mature BOM #

The ADI ZedBoard reference design is described as fully tested and covers nine unique supplies. Two MAX15021 dual-output bucks support core, DDR and I/O roles; MAX15053 supplies an auxiliary rail; MAX1983 and MAX6037A support XADC-related functions; MAX1510 provides DDR termination; and MAX8686 creates a 5 V intermediate rail when the input does not already provide 5 V. The page also states that the regulators can be sequenced at power-up.

This is valuable evidence for Zynq-7000 boards such as an XC7Z020 implementation, but it is a mature reference BOM. A new production design should confirm current lifecycle status, recommended replacements, footprint changes and requalification work for every device. A replacement is not approved merely because its output voltage and headline current match.

Artix UltraScale+: exact rail differences matter #

ADI separates its Artix UltraScale+ minimum-rail concept into AU10P/AU15P and AU20P/AU25P cases:

The official page calls both cases non-hardware-verified. Treat the table as a scoped proposal, then validate ripple, transient response, thermal rise, sequence and fault behavior on the actual board.

Zynq UltraScale+: choose integration style and device range #

ADI publishes both paper designs and validated boards for Zynq UltraScale+. They answer different questions.

The ZCU104 paper reference design presents two alternatives for a ZU7-class platform. The monolithic path uses LTC7131EY-1#PBF for 0.85 V VCCINT, LTC3605AEUF#PBF for VCCINT_VCU/utility roles, LT8652SEV#PBF for auxiliary, I/O and utility rails, LTC3633AEUFD#TRPBF for MGT rails, and LT3045EDD#TRPBF or ADP1753ACPZ-R7 for a low-noise auxiliary role.

The module path uses LTM4676AEY#PBF for VCCINT with digital power-system management and PMBus, then LTM4622EY#PBF, LTM4657EY#PBF, LTM4705, LTM4623EY#PBF and the same low-noise LDO options across the remaining stated rails. This is a topology comparison, not a claim that the module path always uses less area or the monolithic path is always cheaper after inductors, capacitors, thermal copper and validation are counted.

For higher-density devices, the HTG-Z922 reference is stronger board evidence. ADI states that the platform is populated with Zynq UltraScale+ ZU17-2 or ZU19-2 and that its power solution is fully validated. LTM4650 supplies the high-current FPGA core role, LTM4644 covers grouped core, BRAM, processor, GT, DDR, I/O and clock roles in the published mapping, LTM4625 supplies FPGA auxiliary power, and LTC6902 provides clocking for the modules.

Do not generalize either reference beyond its target. AMD's current UltraScale PCB design guidance shows that Zynq UltraScale+ power domains and allowable consolidation vary with the desired power-management flexibility and device features. A ZU7EV video-codec rail plan, a ZU17EG design and a smaller CG device can require different regulator count and isolation.

High-speed transceivers need their own evidence #

The ADI Kintex UltraScale MGT design is intentionally narrower than a full FPGA tree. The DC2340A card plugs into a KCU1250 characterization kit and is published with a maximum output ripple figure of 3.16 mV peak-to-peak for the documented setup.

Its rail map is specific:

• LTM4649 supplies 1 V MGTAVCC;
• LTM4624 supplies 1.2 V MGTAVTT;
• LT3065 supplies 1.8 V MGTAVCCAUX;
• LTC2974 provides four-channel PMBus voltage control, telemetry and sequencing.

This is useful evidence for the noise-sensitive GT subsystem and for a managed-power workflow. It is not a complete Kintex UltraScale production BOM, nor does one lab ripple result cover a changed layout, output network, input bus, transceiver count or measurement bandwidth.

Versal moves the design toward scalable managed power #

This original LimChip redraw uses only the devices and rail roles published in ADI's XCVC1902 reference page. It explains one verified example rather than combining parts from unrelated boards. It is still a functional map, not a production schematic; phase count, current and compensation must follow the actual AMD power estimate.

Versal AI Core XCVC1902: scalable multiphase core power #

ADI describes its Versal AI Core XCVC1902 board as tested and proven for key rails. The core architecture pairs the eight-phase PMBus LTC3888-1 controller with LTC7051 SilentMOS stages and is stated to scale up to 240 A by changing the number of stages.

The same page assigns LTC3636 to several MGT, auxiliary and I/O rails, LT8607 to MGTYVCCAUX, and LTC3634 to DDR sink/source power. Those assignments illustrate three distinct jobs: high-current digitally managed core conversion, medium-current multirail conversion, and specialized low-current or bidirectional memory support.

The 240 A figure is the reference architecture's stated capability, not an XCVC1902 consumption claim. Phase count must come from the actual AMD estimate, transient envelope, thermal design and fault-current strategy.

Versal Prime Gen 2 2VM3858: a current verified minimum-rail example #

ADI's Versal Prime Series Gen 2 design names the 2VM3858 target and labels the minimum-rail design verified. Its published BOM is unusually useful to procurement because it includes complete orderable codes, temperature ranges and quantity:

The exact suffixes matter. Tape-and-reel designation, package, temperature grade and programmed behavior belong in the sourcing BOM, not in an informal note.

Versal HBM: keep the non-hardware-verified boundary #

ADI's Versal HBM design is explicitly non-hardware-verified. It proposes LTC3888-1/LTC7051 for VCCINT, LTC3633A for system intermediate rails, LT8652S for VCCAUX and GTAVCC, LT7200S for VCCO and HBM-core roles, LTC7151S for GTAVTT, ADP125 for auxiliary rails, and optional LTC3617/LTC3618 DDR functions.

That is a valuable architectural shortlist, not production validation. HBM devices combine high power density with memory-specific rails; the design needs AMD scenario data, ADI configuration files, PDN simulation and physical hardware validation before release.

Sequencing and monitoring are system functions #

ADI devices can implement sequencing, telemetry and fault management, but AMD documentation defines what the FPGA requires. Do not infer the permitted sequence from enable-pin convenience.

For UltraScale and UltraScale+ designs, the exact family data sheet and UG583 rail-consolidation guidance govern connections such as VCCINT, VCCINT_IO and VCCBRAM. Speed-grade and low-voltage variants can change which rails may be tied together. For Versal, UG863 directs designers to Power Design Manager for the selected minimum-rail or full-power-management scenario, including voltages, tolerances, grouping and sequence.

Map those requirements into one of three control levels:

1. Enable and power-good chain. Suitable when the device permits a simple fixed sequence and fault response is fully defined. 2. Dedicated sequencer/monitor. ADM1186 can sequence four rails in the Artix concept; MAX34440 adds six-channel PMBus management in the Versal Prime Gen 2 design. 3. Digital power-system management. LTC2974, LTC3888-1, LTC7131 and LTM4676A-class devices add combinations of telemetry, margining, configuration and fault logging, depending on the exact product.

The production test plan should record ramp timing, monotonically rising rails, power-good thresholds, discharge behavior, fault shutdown, retry policy and configuration checksum. Telemetry is not useful unless firmware ownership, PMBus addresses, calibration and alert handling are also released.

Turn the reference design into a controlled BOM #

Decide between modules, monolithic regulators and controller-plus-stage power #

Use the reference topology as a trade-study baseline:

There is no universal “best ADI FPGA regulator.” The correct answer changes with the exact FPGA load, evidence level, board area, thermal environment, production volume and qualification plan.

Release exact orderable codes #

An RFQ should never shorten LTM4676AEY#PBF to “LTM4676,” MAX20860AAFX+ to “MAX20860,” or LTC3888-1 to “LTC3888.” Suffixes may encode package, grade, revision, packing or functional option. Preserve them through AVL, purchase order, incoming inspection and change control.

For configurable digital devices, attach the approved configuration file and checksum. For every device, record:

• manufacturer and complete orderable code;
• rail/function and reference-design source;
• package, temperature grade and qualification requirement;
• programmed option, resistor setting or PMBus configuration;
• approved alternates and the engineering evidence for each;
• lifecycle status checked on the order-release date;
• required date code, lot consistency, traceability and packing condition.

Engineering and buyer RFQ checklist #

• Send the exact AMD-Xilinx OPN, package and speed/temperature grade.
• Include the AMD power estimate and the assumptions used to generate it.
• Identify the closest ADI reference and its evidence status: tested, verified, paper or non-hardware-verified.
• Provide input bus, every rail voltage/current, allowed consolidation and sequence.
• State whether DDR, GT, video-codec, HBM, FMC and board-utility loads are included.
• List complete ADI orderable codes, quantities and approved configuration revisions.
• Confirm telemetry, sequencer, power-good and fault-response ownership.
• Request current lifecycle, traceability, date code, packing and shipment data at quotation time rather than copying old web availability.
• Revalidate the PDN, transient response, thermals and start-up after any FPGA workload, memory, package or regulator substitution.

Conclusion #

ADI's AMD-Xilinx portfolio spans compact integrated rails, low-noise GT supplies, μModule power, digitally managed multiphase cores and dedicated sequencing. Its real advantage is not the length of the component list; it is the number of named, inspectable reference designs across FPGA generations. The engineering discipline is to preserve each design's target and evidence boundary.

For the system-level method that precedes vendor selection, read AMD-Xilinx FPGA Power Delivery: Design Guide. For the corresponding independent FPGA vendor architecture, see Altera FPGA Power Delivery: Design Guide. This ADI article narrows that broader workflow to exact ADI rail roles, orderable codes and sourcing controls.

Before requesting stock, send the FPGA ordering code, power estimate, rail table, reference-design source and qualification requirements. LimChip can then quote the exact BOM while engineering keeps electrical approval separate from commercial availability.

Official references #

• Analog Devices AMD-Xilinx FPGA Power Delivery Solutions
• Analog Devices Spartan-7 Non-Hardware-Verified Design
• Analog Devices ZedBoard Power Reference Design
• Analog Devices Artix UltraScale+ Minimum-Rail Design
• Analog Devices ZCU104 Paper Reference Design
• Analog Devices HTG-Z922 Zynq UltraScale+ Platform
• Analog Devices Xilinx-Tested Kintex UltraScale MGT Power Design
• Analog Devices Versal AI Core XCVC1902 Reference Design
• Analog Devices Versal Prime Series Gen 2 Verified Design
• Analog Devices Versal HBM Non-Hardware-Verified Design
• AMD UltraScale Architecture PCB Design User Guide
• AMD Versal Adaptive SoC Power-Management Scenarios