Decoupling Capacitor Selection: From Target Impedance to a Buildable BOM

Most boards get their decoupling from habit rather than from a calculation. A 100 nF part next to every power pin, a 10 µF somewhere in the corner, a bulk electrolytic near the regulator, and the schematic moves on. That habit survives because it usually works — until the core rail drops to 0.8 V, the load steps in nanoseconds, and the bench shows droop that no amount of extra 100 nF parts will fix.

The gap between the habit and the requirement is not mysterious. A decoupling network is a sizing problem in the frequency domain, and it ends as a purchasing problem with specific ordering codes. This guide walks the whole distance: how to set the budget, how to allocate it across capacitor tiers, why the capacitance printed on the reel is not the capacitance the rail sees, and what has to be frozen in the BOM so a second source does not quietly undo the design.

Start with a budget, not a value #

The regulator is not fast. Its control loop responds over microseconds; the load can change in nanoseconds. Everything in that gap has to come out of capacitance already sitting on the board. So the first question is not "which capacitor" but "how much impedance can this rail tolerate."

The standard first-order tool is target impedance:

Z_target = ΔV_allowed ÷ ΔI_step

A 0.85 V core rail with a ±3% transient allowance gives roughly 25 mV of room. If the device can swing 20 A between idle and full activity, the network must hold roughly 1.3 mΩ across the frequency range where the load actually moves. Change the step to 40 A and the budget halves. This is why high-current FPGAs and accelerators need genuinely different decoupling from a microcontroller board — not because the silicon is exotic, but because the arithmetic is brutal.

Two cautions about that number. First, it is a sizing aid, not a specification: real transients are not a single step, and the allowance has to be shared with DC error, ripple and remote-sense drop. Second, a target impedance is only meaningful together with a frequency range. Holding 1.3 mΩ to 1 MHz is an ordinary design; holding it to 100 MHz on the board is not achievable and is not supposed to be, because the package and die handle that end.

Every capacitor only owns one band #

A capacitor behaves like a capacitor only below its self-resonant frequency. Above it, the part's own inductance dominates and impedance rises again. That single fact is why a decoupling network is a set of tiers rather than a single part, and why "add more 100 nF" stops working at some point.

Read the plot from left to right and the division of labour is clear.

Bulk: the low-frequency reservoir #

Below roughly 100 kHz the regulator loop is still in control, and bulk capacitance covers the handover region while the loop catches up. This is the job of aluminium electrolytic, tantalum and polymer parts — high capacitance per unit cost and volume, relatively high ESR, and no useful behaviour at high frequency. A part such as the KEMET T491X337K010AT — 330 µF, 10 V, 500 mΩ ESR in a 2917 case — is a bulk element, not a decoupling element. So is a EEE-FK1V471SP at 470 µF and 80 mΩ ESR. Their ESR is not purely a defect here: it damps the network, which matters in the next section.

Ceramics: the mid-band workhorse #

From roughly 100 kHz to tens of megahertz the board relies on MLCCs. This is where the familiar values live, and where a GRM188R71H104KA93D — 100 nF, X7R, 0603 — does its work. The important selection variables in this tier are not the capacitance printed on the part. They are dielectric class, case size and how the part is mounted, because those decide both the effective capacitance and the frequency at which the part stops being a capacitor.

Package and on-die: beyond the board's reach #

Above the ceramics, only capacitance inside the package or on the die responds fast enough. Board designers cannot add to this tier; they can only avoid wasting effort trying to cover it. When a device vendor publishes decoupling tables, part of what those tables encode is how much on-package capacitance the device already carries — which is why the same silicon in a different package can carry a different recommendation.

The capacitance you buy is not the capacitance you get #

This is where a lot of otherwise careful designs lose margin. Class II ceramic dielectrics — X5R, X7R, X6S — use barium titanate, and their effective capacitance falls when DC voltage is applied across them. Murata describes the mechanism directly: applied DC voltage locks the spontaneous polarisation in the ferroelectric so it can no longer reverse freely, and the measured capacitance drops as a result. In Murata's own worked example, a 100 µF part rated 6.3 V with 1.8 V applied loses about 10% of its capacitance with X5R characteristics and about 40% with Y5V (Murata, *The voltage characteristics of electrostatic capacitance*). Temperature-compensating dielectrics such as C0G are not affected — Murata's capacitor FAQ states plainly that C0G-type parts "have no DC bias characteristic" (Murata Ceramic Capacitors FAQ).

Two practical consequences follow.

The first is that voltage rating is a derating decision, not just a safety decision. A 22 µF X5R rated 6.3 V used on a 5 V rail is operating deep into its bias curve; the same value at 25 V rating in a larger case keeps far more of its nameplate. Choosing the rating purely by "must exceed the rail voltage" gives a network that meets the schematic and misses the impedance budget.

The second is that the bias loss compounds with temperature drift and ageing. An X7R part is specified within ±15% over its temperature range before any bias is applied. Stack bias loss, temperature drift and tolerance and the worst-case effective value can be a fraction of the nominal. The honest way to handle this is to design with effective capacitance at the operating point — vendor simulation tools publish bias curves per ordering code — and to record that assumption where the next engineer will find it.

There is one piece of good news in the physics. Because bias loss scales with the field across the dielectric, the problem eases as rails drop. Murata notes that for chips operating below about 1 V, DC bias on the supply line is much less pronounced. Core rails are the least affected; the 3.3 V, 5 V and 12 V rails are where the surprises live.

Mounting inductance decides the top of the band #

Once the dielectric question is settled, the remaining variable is inductance — and most of it is not inside the capacitor. The pads, the fanout trace, the vias and the return path through the plane pair form a loop, and the area of that loop sets the series inductance in the path.

This is why case size often matters more than value. A 0402 part has a shorter internal current path than an 0805 of the same capacitance, so it resonates higher and stays useful further up the band. It is also why several small capacitors frequently outperform one large one at high frequency: the parallel paths divide the inductance, while a single part cannot.

The practical rules that fall out of this are unglamorous and effective:

• Place the smallest, highest-frequency parts closest to the power pins, and

let the larger values sit further out.

• Put vias immediately at the pads rather than at the end of a fanout trace,

and use two vias per terminal where the layer count allows.

• Keep the power and ground planes adjacent and close, since the plane pair is

the return path for every one of those loops.

• Treat any change to the layout of a decoupling site as a change to the

electrical design, not as a routing detail.

Device vendors encode a lot of this in their published guidance rather than leaving it to first principles. AMD's UltraScale PCB design guide, for example, publishes decoupling capacitor quantities per device and per package — separate counts for 330 µF, 100 µF, 47 µF and 10 µF elements against specific ordering codes — instead of a single universal rule, and directs designers to its Power Design Manager tool for the per-design scheme (AMD UG583, *UltraScale Architecture PCB Design*). Where such a table exists for the device you are using, it is a far better starting point than a generic ratio.

When adding capacitors makes things worse #

Between any two capacitor tiers there is a frequency where one part has gone inductive and the next has not yet taken over. The inductance of the first and the capacitance of the second form a parallel resonance, and impedance peaks instead of falling. Those are the humps in the first diagram, and they are the most common reason a network with plenty of total capacitance still fails its budget.

Anti-resonance is worth understanding because the intuitive fix makes it worse. Adding more of the same value deepens the notch at that value and sharpens the peak beside it. What actually helps is different in kind:

• Keep the number of distinct values modest and spaced roughly a decade apart,

so the tiers overlap instead of leaving gaps.

• Do not chase an ultra-low-ESR part everywhere. Some series resistance damps

the peak; this is one reason a polymer or tantalum element earns its place alongside ceramics rather than being replaced by them.

• Verify in simulation before committing the layout. Impedance profiles are

cheap to model and expensive to discover on the bench.

Turning the network into a BOM that survives #

A decoupling design is only as good as the ordering codes it becomes. Once the tiers are set, the properties that must be frozen are broader than most BOM lines record.

The substitution rule follows from that table: same capacitance is not the same part. Two 10 µF 0805 X5R capacitors from different series can differ materially in bias curve and ESL, and swapping one for the other on a core rail is an electrical change even though the schematic value is identical. For rails where the impedance budget is tight, name the approved series and case size in the BOM and treat alternates as requiring engineering review. For non-critical bypass positions, a wider alternate list is reasonable and keeps the board buildable.

That distinction matters commercially as well as technically. MLCC supply is not a stable background condition — 2026 has already seen vendor price actions and lead-time movement across the passive market, which we covered in the MLCC price hike watch. A BOM that locks every capacitor position to a single ordering code is fragile; a BOM that locks nothing is a power-integrity risk. The workable middle is to identify the small number of positions where the bias curve, ESR or case size is genuinely load-bearing, freeze those, and give purchasing real freedom everywhere else. When you do source the frozen positions, confirm the full ordering code, date code and reel condition rather than the value alone — capacitor part numbers encode dielectric, rating and tolerance in suffixes that are easy to lose in a spreadsheet.

So how do you choose decoupling capacitors? #

Not by value first. Set an impedance budget from the rail tolerance and the real transient step, and decide the frequency range the board is actually responsible for. Allocate that budget across three tiers — bulk for the handover from the regulator, ceramics for the mid band, package capacitance for everything above — and accept that the top of the band is not yours to fix. Choose ceramics by dielectric class, voltage rating and case size so the effective capacitance under bias, not the nameplate value, meets the budget. Control mounting inductance through via placement and case size, because that is what sets the high-frequency ceiling. Check for anti-resonance instead of assuming more capacitance is always safer. Then write the result into the BOM with enough specificity that a substitution cannot silently change the impedance profile.

Done in that order, the network is defensible on the bench and buildable in volume. Done as a habit, it is a guess that happens to have worked on the last board.

If you are specifying the passive side of a power design and want to confirm what is actually available against the ordering codes you have chosen, the passive component inventory lists published ceramic, tantalum and aluminium parts with their case, rating and dielectric detail.

Sources #

• Murata, *The voltage characteristics of electrostatic capacitance* — DC bias mechanism and worked X5R/Y5V capacitance-loss examples.
• Murata Ceramic Capacitors FAQ: DC bias characteristic — dielectric classes affected by DC bias; C0G behaviour.
• AMD UG583, *UltraScale Architecture PCB Design* — Decoupling Capacitors — per-device, per-package decoupling capacitor quantity tables and Power Design Manager guidance.