HBM Explained: What It Is, the Three Manufacturing Gates and the Market

What HBM actually is #

High Bandwidth Memory (HBM) is a stack of DRAM dies bonded vertically with through-silicon vias (TSV), mounted next to a processor on a silicon interposer. Instead of sending data over a narrow, long trace to a discrete DDR module, HBM places a very wide memory bus (1024–2048 bits today) a millimeter from the compute die. That short, fat path is why a single HBM stack can deliver several hundred GB/s to over 1 TB/s of bandwidth while consuming far less power than an equivalent GDDR or DDR interface.

For readers who want the pin-out and bandwidth-path detail versus DDR4/DDR5, the separate architecture comparison covers that directly. This article is about the harder question: how HBM is actually built, why so few companies can build it, and what that means for sourcing.

The three manufacturing gates #

An HBM stack is not one product but the output of three separate, sequentially dependent manufacturing capabilities. Miss any one and there is no HBM — regardless of how much packaging capacity or capital you have.

Gate 1 — the advanced DRAM die #

The base dies in an HBM stack are not commodity DRAM. HBM3E is built on a ~1b nm-class DRAM process; HBM4 pushes toward 1c nm and beyond. These are the most advanced DRAM nodes in production, several generations ahead of the mainstream DDR4/DDR5 used in PCs and servers.

Gate 2 — TSV stacking #

Once the thin DRAM dies exist, they must be stacked and connected with through-silicon vias. The vias are extremely high aspect ratio — typically 10:1 or more — and the holes must be etched and filled with copper with essentially zero voids, because a single bad connection inside a stacked die cannot be reworked. That step depends on best-in-class plasma etchers (Lam Research and Tokyo Electron are the dominant suppliers) and advanced electroplating equipment.

Public reporting indicates that much of this equipment falls within the scope of US semiconductor export controls introduced in October 2022, which is the second reason the stacking capability is concentrated: the tools themselves are hard to acquire at the leading edge.

Gate 3 — CoWoS advanced packaging #

Even with stacked HBM dies in hand, they are useless until integrated with the GPU or accelerator on a silicon interposer. That integration is CoWoS, a 2.5D platform that is TSMC's proprietary technology. There is no open, licensable equivalent; the interposer line width and inter-die interconnect density set the practical ceiling on how many HBM stacks a chip can carry.

China's advanced-packaging leaders — Changjiang Electronics (JCET), Tongfu Microelectronics and Huahong — primarily offer FC-BGA and 2.5D solutions whose interposer minimum line width and interconnect density trail CoWoS by an estimated 2–3 generations. Policy support for Chiplet and 3D packaging is accelerating domestic investment, and Huawei and SMIC have increased HBM self-sufficiency work, but the gap at this gate is structural rather than merely a matter of spend.

LimChip analysis: optimistic industry estimates place a Chinese HBM2E-class capability somewhere in the 2028–2030 window, with HBM4-parity still further out. The three gates must be cleared *in order* — a fast packaging line cannot compensate for a missing leading-edge DRAM node, and leading-edge dies cannot ship without the stacking and CoWoS steps.

Who controls the HBM market #

Supply is not just concentrated; it is a near-monopoly held by three companies, and no fourth has reached mass production.

• SK hynix — the leader. Industry estimates place SK hynix above 50% of

HBM supply. It was first to volume HBM3E and is ramping HBM4, and it is the primary HBM supplier to NVIDIA.

• Samsung — the challenger. The larger memory maker by DRAM volume, but

behind on HBM3E yield and volume; it is working to close the gap and secure accelerator qualification.

• Micron — the tech leap. Entered HBM later but skipped ahead to HBM3E and

is developing HBM4, betting that a later, cleaner entry can win share as capacity expands.

The critical point for buyers: outside these three, no company mass-produces HBM. The barrier is not only capital — it is the combined mastery of leading-edge DRAM, TSV stacking and CoWoS-class integration. That is why HBM scarcity during the AI build-out has been *structural*, not a normal cyclical tightness that a new fab can relieve within a year or two.

What this means for buyers #

HBM does not sit in a distributor's general stock the way a DDR4 SODIMM or an industrial NOR flash does. It is allocated by the three suppliers directly to accelerator makers, and the accelerator maker's CoWoS capacity — not the DRAM supply alone — sets the real ceiling. A few practical implications:

• **Treat HBM lead times as tied to the accelerator program, not to a memory

datasheet.** When you source an AI server or accelerator module, the HBM is already committed inside that program's allocation.

• Second-source expectations should be realistic. SK hynix, Samsung and

Micron are not interchangeable drop-ins at the stack level; qualification is multi-quarter and bounded by CoWoS, not just DRAM.

• Watch the packaging bottleneck, not only the memory. CoWoS capacity

committed through 2027 is the gating factor for how much HBM actually reaches boards — the dedicated packaging article tracks that directly.

• For designs that do not need HBM bandwidth, DDR5 and GDDR-class memory

remain the pragmatic, available choice; the memory glossary and 2026 DRAM outlook help frame that trade-off.

Conclusion #

HBM is a stacked, interposer-integrated memory whose difficulty is not any single step but the *sequence* of three: a leading-edge DRAM node, high aspect-ratio TSV stacking, and TSMC's CoWoS packaging. Each gate is individually hard and collectively self-reinforcing, which is why supply stays in the hands of SK hynix, Samsung and Micron — and why no fourth supplier has emerged. For buyers, the practical takeaway is to plan HBM availability around accelerator programs and CoWoS capacity, keep DDR5/GDDR as the available default where bandwidth allows, and treat any "new HBM source" claim with the three-gate test above before counting on it in a BOM.

Sources #

• SK hynix — HBM product information
• Samsung Semiconductor — memory and HBM
• Micron — HBM and advanced memory
• TSMC — CoWoS advanced packaging
• US Bureau of Industry and Security — export control information
• Lam Research — etch and deposition systems
• Tokyo Electron — semiconductor production equipment
• TrendForce — HBM market share and supply tracking

Market-share and China-capability statements in this article are industry estimates and analyst views, not LimChip measurements; process-node and export-control facts are drawn from public manufacturer and regulator disclosures.