Why the framebuffer memory choice still matters #

Every GPU, AI inference accelerator, game console and automotive SoC that has to move large textures, weights or feature maps needs high-bandwidth local memory sitting next to the compute die. That "VRAM" is almost always GDDR, and the generation you pick sets a hard ceiling on how fast the processor can be fed.

For a board designer the decision between GDDR6, GDDR6X and GDDR7 is not a spec-sheet tick. It is a bandwidth-versus-power-versus-cost-versus-supply trade-off that locks in the PHY, the PCB layout, the thermal budget and, often, the bill of materials for the whole product life. This guide walks through what actually separates the three current options and how to pick one.

What GDDR is — and what it is not #

GDDR (Graphics Double Data Rate SGRAM) is a discrete DRAM packaged beside the GPU on the same board, connected by point-to-point PCB traces and tuned for raw bandwidth rather than capacity or latency. It is easy to confuse the generations with the rest of the memory family, so it is worth separating them:

  • DDR5 / LPDDR5 is CPU and SoC main memory, mounted off-package, optimized

for capacity and latency at a lower pin data rate.

  • HBM (HBM2E / HBM3 / HBM3E / HBM4) is 3D-stacked DRAM on a silicon

interposer with a 1024-bit or wider bus — extreme bandwidth and efficiency, but high cost and 2.5D integration complexity.

  • GDDR sits between the two: cheaper and far easier to route than HBM, yet

delivering several times the bandwidth per device of DDR/LPDDR.

All three GDDR generations below are JEDEC SGRAM families with a ×32-bit interface per device, but they differ sharply in signaling and speed.

The three options at a glance #

AttributeGDDR6GDDR6XGDDR7
Introduction / status~2018, broadly standardizedMicron + NVIDIA PAM4 variant, 2020JEDEC JESD239 published Mar 2024
SignalingNRZ (PAM2, 2 levels)PAM4 (4 levels)PAM3 (3 levels)
Max data rate per pin16 Gbps (some 18 Gbps parts)19–24 Gbps32 Gbps initial; up to 48 Gbps roadmap
Bandwidth per device (×32 bus)~64 GB/s at 16 Gbps~84–96 GB/sup to 192 GB/s (JESD239)
I/O voltage (VDDQ)1.35 / 1.25 V1.35 / 1.25 V1.2 V (Samsung 1.1 V variant)
Density per device8–16 Gb8–16 Gb16–32 Gb
Independent channels per device224
On-die ECCNoNoYes (ODECC)
SourcingMulti-source (Samsung, SK hynix, Micron)Essentially Micron-only for yearsMulti-source (Samsung, Micron, SK hynix in production)

The per-pin data rates are vendor-documented: Micron's ultra-bandwidth brief states GDDR6 at 16 Gbps/pin and GDDR6X reaching 21 Gbps at launch with a 24 Gbps path on the roadmap. JEDEC's JESD239 press release (5 March 2024) specifies GDDR7 at up to 192 GB/s per device, an initial 32 Gbps/pin rate and a future 48 Gbps/pin ceiling, with Samsung, Micron and SK hynix all in mass production.

How bandwidth actually scales on a board #

Total card bandwidth is the data rate per pin, times the bus width per device, divided by eight, times the number of devices:

``` bandwidth = (data_rate_per_pin × 32 / 8) × device_count ```

A 384-bit board with twelve GDDR6 devices at 16 Gbps reaches roughly 768 GB/s. Twelve GDDR6X devices at 21 Gbps clear 1 TB/s. GDDR7 already delivers up to 192 GB/s from a single device, so a designer can hit the same ceiling with fewer parts — freeing board space, cost and power. The two real levers are the pin data rate (set by signaling) and the device count (set by board area and budget), and every generation change moves both.

Power and signal-integrity trade-offs #

The signaling scheme is where the generations diverge most for a hardware team:

  • GDDR6 (NRZ / PAM2) transmits one bit per symbol. It is the simplest to

equalize and route, but it caps out near 16 Gbps/pin.

  • GDDR6X (PAM4) packs two bits per symbol using four voltage levels, which is

what pushes per-pin rate to 19–24 Gbps. The cost is more equalization, tighter signal-to-noise margin and higher overall device power — Micron notes lower pJ/bit at the link but higher total draw because the part runs faster.

  • GDDR7 (PAM3) uses three levels. JEDEC describes PAM3 as carrying three bits

over two cycles versus NRZ's two bits over two cycles, with better SNR and energy efficiency than PAM4 at high frequency. That is what lets GDDR7 reach 32 Gbps at 1.2 V with more than 50% better power efficiency than GDDR6, while on-die ECC and a lower-thermal-resistance package address reliability and heat.

Faster signaling also means the replacement is never a drop-in. The PHY, PCB trace impedance, termination, training firmware and eye-diagram margins all change between NRZ, PAM4 and PAM3. Swapping a generation is a re-validation, not a BOM edit.

Sourcing and second-source risk #

This is where procurement teams get surprised:

  • GDDR6X was effectively a single-source part (Micron, with NVIDIA as launch

partner) for years. A design locked to it carries real supply and negotiation risk.

  • GDDR6 and GDDR7 are multi-source, but cross-vendor pin-compatibility is not

guaranteed — different ball-map, timing, VPP and training mean a second-source swap needs SI re-validation and an engineering change, not just a substitute line.

  • Even "commodity" GDDR sees allocation and long lead times during memory up-

cycles driven by AI demand. Confirm date code, reel/tray condition, MSL and traceability before committing stock.

The practical buyer action is to lock the exact ordering code (density, speed grade, package), request samples early, and qualify at least two vendors wherever the design permits.

When to pick which #

  • GDDR6 — the mature, widely available, cost-sensitive default. More than

enough for mainstream 4K gaming, industrial GPUs and many inference cards. Choose it unless the bandwidth ceiling forces a higher generation.

  • GDDR6X — only when you must match an NVIDIA-aligned Ampere-era board or need

the highest per-pin rate a PAM4 part offers. Accept the single-source concentration risk as a conscious trade.

  • GDDR7 — the forward choice for new high-bandwidth designs: Blackwell-class

GPUs, AI inference accelerators, automotive and edge accelerators that need maximum bandwidth per watt. It is multi-source, adds on-die ECC for reliability, and repays the PAM3 PHY and thermal planning with the best efficiency of the three.

Conclusion #

Choosing between GDDR6, GDDR6X and GDDR7 comes down to four questions: how much bandwidth your compute actually needs (which sets the pin data rate and device count), how much power and board heat you can spare (PAM3 / GDDR7 wins), how much supply risk you will accept (avoid single-source lock-in; prefer multi-source GDDR6 or GDDR7), and how much qualification effort you can fund (every generation change is a PHY and PCB re-validation, not a swap). For new designs, GDDR7 is the bandwidth-per-watt leader and the safe multi-source path; GDDR6 remains the pragmatic default; GDDR6X is a niche, NVIDIA-aligned option with real sourcing concentration to plan around.

Sources #

  • JEDEC — *JESD239 Graphics Double Data Rate (GDDR7) SGRAM published* (press release, 5 March 2024).
  • Micron — *The Demand for Ultra-Bandwidth Solutions* technical brief (GDDR6 16 Gbps/pin; GDDR6X 21 Gbps launch, up to 24 Gbps roadmap).
  • Samsung / SK hynix / Micron — GDDR7 mass-production announcements (32 Gbps/pin, PAM3 signaling, on-die ECC).
  • LimChip — HBM vs DDR4/DDR5: architecture and sourcing and the memory glossary for the wider DRAM family context.
Use the manufacturer datasheet and approved engineering documents for final design decisions.

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