MLCC Dielectric Classes Explained: C0G, X7R, X5R and What DC-Bias Derating Really Means

Why MLCCs show up everywhere #

Multilayer ceramic capacitors are the default decoupling and bypass part on almost every modern board: tiny, cheap, low equivalent series resistance and inductance, and stable at high frequency. That ubiquity is exactly why a buyer or EMS planner needs to understand what the dielectric code on the bag actually means — because not all ceramics behave the same once they are soldered onto a powered board.

What the dielectric code tells you #

The letters and numbers after the size code in a ceramic capacitor's ordering code encode the dielectric class. The industry splits MLCC dielectrics into two families:

• Class 1 — temperature-compensating, very stable. The common code is C0G (also called NP0).
• Class 2 — high dielectric constant, high capacitance per volume, but with real trade-offs. The common codes are X7R, X5R, Y5V (and newer X6S, X7S, X8R, and similar).

Class 1: C0G / NP0 #

C0G is the reference dielectric. Its capacitance barely moves with temperature, voltage, frequency or aging:

• Temperature coefficient is effectively ±30 ppm/°C across the whole −55 °C to +125 °C range.
• No meaningful DC-bias loss, no significant voltage coefficient, near-zero aging.
• Very low losses, so it is the right choice for timing, filtering, RF matching and precision analog paths.

The cost is density. A C0G part tops out at modest values (typically nanofarads to a few microfarads even in larger cases), so it is poor for bulk decoupling.

Class 2: X7R, X5R, Y5V #

Class 2 dielectrics pack far more capacitance into the same case, which is why they dominate bulk decoupling and coupling. But the extra density comes with behavior the part-number label does not print in plain language:

• X7R — ±15% capacitance shift over −55 °C to +125 °C.
• X5R — ±15% over −55 °C to +85 °C.
• Y5V — +22% / −82% over −30 °C to +85 °C, and it drifts fast with voltage and age.

So an X7R that reads "10 µF" at 25 °C and zero volts may read materially less under real operating conditions. That is normal for the dielectric — the surprise is only when the reviewer assumed the label value holds everywhere.

Reading the EIA temperature code #

The first character is the low-end temperature, the digit is the high-end temperature, and the final character is the capacitance tolerance over that band:

So X7R = −55 → +125 °C at ±15%; X5R = −55 → +85 °C at ±15%; Y5V = −30 → +85 °C with the wide +22 / −82% swing.

The DC-bias derating trap #

This is the part that bites design and sourcing reviews most often. Class 2 ceramics lose capacitance as the applied DC voltage rises. A 50 V-rated X7R in a 0402 or 0603 case can lose 20–50% of its marked value at half its rated voltage, and more near full rating; larger cases and lower-voltage-rated parts often lose less, but the only trustworthy number is the vendor's DC-bias curve for that exact size and voltage.

Two practical consequences:

1. Don't spec a 50 V part and assume 50 V headroom. If your rail is 12 V, a 25 V or 16 V part in the right case may keep more of its capacitance than a 50 V part of the same value, depending on size. The rating is a reliability ceiling, not a derating floor. 2. Check the curve, not the label, for bulk decoupling. When a PMIC or SoC calls for "10 µF effective," the effective value under bias is what matters. A board that passes at 25 °C no-load can fall out of spec once the rail is live.

How to read a vendor datasheet for a ceramic cap #

A useful review checks four things beyond the headline value:

• Dielectric class — confirm C0G vs X7R / X5R / Y5V from the code; do not infer it from the capacitance.
• DC-bias curve — for class 2 parts, read capacitance vs voltage at your operating point.
• Temperature and aging — class 2 parts age (class 1 do not), and the tolerance band assumes the full rated band.
• Rated voltage vs applied — derate for margin, but understand that derating changes effective capacitance too.

Sourcing and qualification checks #

The two published examples in the catalogue illustrate the split: GRM188R71H104KA93D (Murata, 0603, X7R, 100 nF) and CL31A226KAHNNNE (Samsung, 1206, X5R, 22 µF) are both class 2 and both need a DC-bias check before they are treated as their label value.

Conclusion #

Pick C0G / NP0 when stability matters — timing, RF and precision analog — and accept its lower density. Pick X7R or X5R for bulk decoupling and coupling where size and cost win, but design and buy against the effective capacitance under voltage and temperature, not the printed number. Y5V belongs only where the budget is tight and the tolerance can be absorbed. Before any purchase, confirm the dielectric class, read the vendor's DC-bias curve for the exact case, and re-qualify any "equivalent" substitution.