Why mixed-voltage boards need a translator #
A modern board rarely runs on a single IO voltage. A microcontroller may use 1.8 V or 1.2 V cores, a sensor bank runs at 3.3 V, legacy CAN or display logic still expects 5 V, and an FPGA bank can sit anywhere in between. Connecting those rails directly causes two failure modes: the lower-voltage device's input gets overdriven and latches or breaks, or the higher-voltage output never crosses the lower device's input threshold and the link is simply dead.
A logic voltage-level translator sits between the two domains and shifts each signal to the correct swing. The selection problem is not "do I need one" — it is "which architecture fits this bus".
Two translator architectures #
Most off-the-shelf translators fall into two groups, and the choice between them drives almost every other parameter.
Direction-controlled (dual-supply, DIR pin). These parts have separate VCCA and VCCB rails and one or more direction-control inputs. A 16-bit part such as the published `SN74ALVC164245DGGR` bridges two independent low-voltage domains through VCCA/VCCB rails rated 1.65–3.6 V each, with roughly ±24 mA output drive in a 48-TSSOP. Because the direction is fixed by a pin, timing is predictable and the driver can be strong — good for wide, fast parallel buses.
Auto-direction-sensing (pass-transistor + pull-up). Parts such as the published `TXS0108EPWR` use an internal pass transistor with pull-up resistors and sense the driving side, so no DIR pin is needed. The TXS0108EPWR covers 1.2 V to 5.5 V logic domains, reaches up to 110 Mbps in push-pull mode, and ships in a 20-TSSOP. The trade-off is weaker drive and a speed ceiling on open-drain lines (typically a few Mbps), because the pull-ups must charge the bus.
Key selection parameters #
| Parameter | Why it matters | What to confirm |
|---|---|---|
| Voltage range (VCCA / VCCB) | Must span both domains on each rail | Min and max of each side; some parts are asymmetric |
| Direction scheme | Determines pin count and timing | DIR-controlled for known direction; auto-sense for dynamic |
| Data rate | Bus must meet link budget | Push-pull vs open-drain ceiling (e.g. TXS ~110 Mbps push-pull) |
| Drive strength / load | Capacitive bus and fan-out | Direction-controlled parts drive heavier loads |
| Ioff / partial-power-down | Prevents back-powering an off rail | Required in hot-swap and modular cards |
| Open-drain support | I2C, SMBus need it | Auto-sense supports it; controlled parts are push-pull only |
| ESD, package, MSL | Assembly and field reliability | Grade, body size, moisture sensitivity |
Which architecture to choose #
Match the bus behaviour, not the headline speed:
- I2C, SMBus, 1-Wire — open-drain by definition, so an auto-sensing
translator (TXS family) or an external pull-up arrangement is the natural fit; a direction-controlled buffer cannot serve an open-drain line.
- UART, SPI at moderate speed — either works; auto-sense saves pins,
direction-controlled gives cleaner timing if the bus is fast.
- Parallel memory, FPGA GPIO, wide data buses — direction-controlled
dual-supply transceivers win on drive and predictable skew across many bits.
- Hot-swap or modular mezzanine cards — require Ioff so an unpowered card
cannot be back-driven through the translator.
Sourcing and qualification notes #
Translator selection is easy to get wrong at the ordering-code level:
- Match the full orderable code. Package, reel versus tube, and grade all
matter. Automotive builds need the Q-suffix variant (for example `TXS0102QDCURQ1`), not the commercial equivalent.
- Don't assume pin-compatible cross-vendor drops. Auto-direction parts
from different vendors differ in pull-up strength, edge-rate control and maximum open-drain speed; a silent substitution can break an I2C bus.
- Confirm lot condition before RFQ. High-run logic is a common remarked or
refurbished target; ask for date code, lot traceability and MSL with the quote.
- Verify the voltage window against your actual rails. A part rated
1.65–3.6 V on each side will not help a 1.2 V core talk to a 5 V peripheral.
Practical selection checklist #
1. Are there two distinct voltage domains? Confirm each rail's min/max. 2. Is the direction known at design time? Known → direction-controlled; dynamic → auto-sense. 3. What is the sustained bus speed? Above roughly 50 Mbps sustained → direction-controlled. 4. Is the bus open-drain (I2C/SMBus)? Then auto-sense or external pull-ups. 5. Can a card be unpowered while the bus is live? Require Ioff. 6. Is this an automotive or extended-temperature build? Require the Q1 / extended-grade suffix.
Conclusion #
Pick a direction-controlled dual-supply transceiver (for example a 16-bit bus part such as `SN74ALVC164245DGGR`) when the bus is wide, fast and push-pull and the direction is fixed at design time. Pick an auto-sensing translator (for example the 8-bit `TXS0108EPWR`) when the bus is open-drain or mixed-signal at low-to-moderate speed and saving the DIR pin matters more than maximum bandwidth. In both cases, confirm the full ordering code, the exact voltage window and the lot condition with your supplier before the build — the translator is cheap, but a wrong voltage swing can take the whole link down.
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